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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-10 18:51:15 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-10 18:51:15 -0400 |
| commit | c44e3ed539e4fc17d6bcb5eaecb894a94de4cc5f (patch) | |
| tree | dbc31370fbc5196e090708341f3ca4c4dca7f41e /Documentation | |
| parent | 7dc3ca39cb1e22eedbf1207ff9ac7bf682fc0f6d (diff) | |
| parent | 5095f59bda6793a7b8f0856096d6893fe98e0e51 (diff) | |
Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86: cpu_debug: Remove model information to reduce encoding-decoding
x86: fixup numa_node information for AMD CPU northbridge functions
x86: k8 convert node_to_k8_nb_misc() from a macro to an inline function
x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions
x86/docs: add description for cache_disable sysfs interface
x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled
x86: cacheinfo: replace sysfs interface for cache_disable feature
x86: cacheinfo: use cached K8 NB_MISC devices instead of scanning for it
x86: cacheinfo: correct return value when cache_disable feature is not active
x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-devices-cache_disable | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-devices-cache_disable b/Documentation/ABI/testing/sysfs-devices-cache_disable new file mode 100644 index 000000000000..175bb4f70512 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-cache_disable | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X | ||
| 2 | Date: August 2008 | ||
| 3 | KernelVersion: 2.6.27 | ||
| 4 | Contact: mark.langsdorf@amd.com | ||
| 5 | Description: These files exist in every cpu's cache index directories. | ||
| 6 | There are currently 2 cache_disable_# files in each | ||
| 7 | directory. Reading from these files on a supported | ||
| 8 | processor will return that cache disable index value | ||
| 9 | for that processor and node. Writing to one of these | ||
| 10 | files will cause the specificed cache index to be disabled. | ||
| 11 | |||
| 12 | Currently, only AMD Family 10h Processors support cache index | ||
| 13 | disable, and only for their L3 caches. See the BIOS and | ||
| 14 | Kernel Developer's Guide at | ||
| 15 | http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf | ||
| 16 | for formatting information and other details on the | ||
| 17 | cache index disable. | ||
| 18 | Users: joachim.deguara@amd.com | ||