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authorSean MacLennan <smaclennan@pikatech.com>2008-12-10 08:16:34 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-01-05 11:42:44 -0500
commita808ad3b0d28411e2838117c5b2ae680ae42483c (patch)
treeedd291f3873ca95e0fb2a434034d30669666b6f4 /Documentation
parent647b0d3854d776485faea9de7e7ed7fd4bdc6f20 (diff)
[MTD] [NAND] ndfc driver
The current ndfc driver only compiles under arch/ppc. This arch was removed from the kernel. I notice the event entry for the ndfc in Kconfig has been removed in 2.6.28. This patch converts the ndfc to a proper OF (OpenFirmware) driver. I can give a working example of the DTS if needed. The patch has been in production use on the PIKA Warp Appliance and is in use by others. The Warp basically boots from NAND, so the ndfc driver is very important to us. Signed-off-by: Sean MacLennan <smaclennan@pikatech.com> Acked-By: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/powerpc/dts-bindings/4xx/ndfc.txt39
1 files changed, 39 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/4xx/ndfc.txt b/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
new file mode 100644
index 000000000000..869f0b5f16e8
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1AMCC NDFC (NanD Flash Controller)
2
3Required properties:
4- compatible : "ibm,ndfc".
5- reg : should specify chip select and size used for the chip (0x2000).
6
7Optional properties:
8- ccr : NDFC config and control register value (default 0).
9- bank-settings : NDFC bank configuration register value (default 0).
10
11Notes:
12- partition(s) - follows the OF MTD standard for partitions
13
14Example:
15
16ndfc@1,0 {
17 compatible = "ibm,ndfc";
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 nand {
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 partition@0 {
29 label = "kernel";
30 reg = <0x00000000 0x00200000>;
31 };
32 partition@200000 {
33 label = "root";
34 reg = <0x00200000 0x03E00000>;
35 };
36 };
37};
38
39