diff options
author | Mathieu Poirier <mathieu.poirier@linaro.org> | 2014-11-12 18:36:59 -0500 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-11-26 22:27:29 -0500 |
commit | 799656de6f6587cecc0b05477501e41c211a75fa (patch) | |
tree | e98db4f9b186613c99b36f9d8cf4b3ba34555959 /Documentation | |
parent | 7a25ec8e481e9c14de13dcacca0d8ee33bfe5f3c (diff) |
coresight: bindings for coresight drivers
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/coresight.txt | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt new file mode 100644 index 000000000000..d790f49066f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight.txt | |||
@@ -0,0 +1,204 @@ | |||
1 | * CoreSight Components: | ||
2 | |||
3 | CoreSight components are compliant with the ARM CoreSight architecture | ||
4 | specification and can be connected in various topologies to suit a particular | ||
5 | SoCs tracing needs. These trace components can generally be classified as | ||
6 | sinks, links and sources. Trace data produced by one or more sources flows | ||
7 | through the intermediate links connecting the source to the currently selected | ||
8 | sink. Each CoreSight component device should use these properties to describe | ||
9 | its hardware characteristcs. | ||
10 | |||
11 | * Required properties for all components *except* non-configurable replicators: | ||
12 | |||
13 | * compatible: These have to be supplemented with "arm,primecell" as | ||
14 | drivers are using the AMBA bus interface. Possible values include: | ||
15 | - "arm,coresight-etb10", "arm,primecell"; | ||
16 | - "arm,coresight-tpiu", "arm,primecell"; | ||
17 | - "arm,coresight-tmc", "arm,primecell"; | ||
18 | - "arm,coresight-funnel", "arm,primecell"; | ||
19 | - "arm,coresight-etm3x", "arm,primecell"; | ||
20 | |||
21 | * reg: physical base address and length of the register | ||
22 | set(s) of the component. | ||
23 | |||
24 | * clocks: the clock associated to this component. | ||
25 | |||
26 | * clock-names: the name of the clock as referenced by the code. | ||
27 | Since we are using the AMBA framework, the name should be | ||
28 | "apb_pclk". | ||
29 | |||
30 | * port or ports: The representation of the component's port | ||
31 | layout using the generic DT graph presentation found in | ||
32 | "bindings/graph.txt". | ||
33 | |||
34 | * Required properties for devices that don't show up on the AMBA bus, such as | ||
35 | non-configurable replicators: | ||
36 | |||
37 | * compatible: Currently supported value is (note the absence of the | ||
38 | AMBA markee): | ||
39 | - "arm,coresight-replicator" | ||
40 | |||
41 | * id: a unique number that will identify this replicator. | ||
42 | |||
43 | * port or ports: same as above. | ||
44 | |||
45 | * Optional properties for ETM/PTMs: | ||
46 | |||
47 | * arm,cp14: must be present if the system accesses ETM/PTM management | ||
48 | registers via co-processor 14. | ||
49 | |||
50 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the | ||
51 | source is considered to belong to CPU0. | ||
52 | |||
53 | * Optional property for TMC: | ||
54 | |||
55 | * arm,buffer-size: size of contiguous buffer space for TMC ETR | ||
56 | (embedded trace router) | ||
57 | |||
58 | |||
59 | Example: | ||
60 | |||
61 | 1. Sinks | ||
62 | etb@20010000 { | ||
63 | compatible = "arm,coresight-etb10", "arm,primecell"; | ||
64 | reg = <0 0x20010000 0 0x1000>; | ||
65 | |||
66 | coresight-default-sink; | ||
67 | clocks = <&oscclk6a>; | ||
68 | clock-names = "apb_pclk"; | ||
69 | port { | ||
70 | etb_in_port: endpoint@0 { | ||
71 | slave-mode; | ||
72 | remote-endpoint = <&replicator_out_port0>; | ||
73 | }; | ||
74 | }; | ||
75 | }; | ||
76 | |||
77 | tpiu@20030000 { | ||
78 | compatible = "arm,coresight-tpiu", "arm,primecell"; | ||
79 | reg = <0 0x20030000 0 0x1000>; | ||
80 | |||
81 | clocks = <&oscclk6a>; | ||
82 | clock-names = "apb_pclk"; | ||
83 | port { | ||
84 | tpiu_in_port: endpoint@0 { | ||
85 | slave-mode; | ||
86 | remote-endpoint = <&replicator_out_port1>; | ||
87 | }; | ||
88 | }; | ||
89 | }; | ||
90 | |||
91 | 2. Links | ||
92 | replicator { | ||
93 | /* non-configurable replicators don't show up on the | ||
94 | * AMBA bus. As such no need to add "arm,primecell". | ||
95 | */ | ||
96 | compatible = "arm,coresight-replicator"; | ||
97 | /* this will show up in debugfs as "0.replicator" */ | ||
98 | id = <0>; | ||
99 | |||
100 | ports { | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <0>; | ||
103 | |||
104 | /* replicator output ports */ | ||
105 | port@0 { | ||
106 | reg = <0>; | ||
107 | replicator_out_port0: endpoint { | ||
108 | remote-endpoint = <&etb_in_port>; | ||
109 | }; | ||
110 | }; | ||
111 | |||
112 | port@1 { | ||
113 | reg = <1>; | ||
114 | replicator_out_port1: endpoint { | ||
115 | remote-endpoint = <&tpiu_in_port>; | ||
116 | }; | ||
117 | }; | ||
118 | |||
119 | /* replicator input port */ | ||
120 | port@2 { | ||
121 | reg = <0>; | ||
122 | replicator_in_port0: endpoint { | ||
123 | slave-mode; | ||
124 | remote-endpoint = <&funnel_out_port0>; | ||
125 | }; | ||
126 | }; | ||
127 | }; | ||
128 | }; | ||
129 | |||
130 | funnel@20040000 { | ||
131 | compatible = "arm,coresight-funnel", "arm,primecell"; | ||
132 | reg = <0 0x20040000 0 0x1000>; | ||
133 | |||
134 | clocks = <&oscclk6a>; | ||
135 | clock-names = "apb_pclk"; | ||
136 | ports { | ||
137 | #address-cells = <1>; | ||
138 | #size-cells = <0>; | ||
139 | |||
140 | /* funnel output port */ | ||
141 | port@0 { | ||
142 | reg = <0>; | ||
143 | funnel_out_port0: endpoint { | ||
144 | remote-endpoint = | ||
145 | <&replicator_in_port0>; | ||
146 | }; | ||
147 | }; | ||
148 | |||
149 | /* funnel input ports */ | ||
150 | port@1 { | ||
151 | reg = <0>; | ||
152 | funnel_in_port0: endpoint { | ||
153 | slave-mode; | ||
154 | remote-endpoint = <&ptm0_out_port>; | ||
155 | }; | ||
156 | }; | ||
157 | |||
158 | port@2 { | ||
159 | reg = <1>; | ||
160 | funnel_in_port1: endpoint { | ||
161 | slave-mode; | ||
162 | remote-endpoint = <&ptm1_out_port>; | ||
163 | }; | ||
164 | }; | ||
165 | |||
166 | port@3 { | ||
167 | reg = <2>; | ||
168 | funnel_in_port2: endpoint { | ||
169 | slave-mode; | ||
170 | remote-endpoint = <&etm0_out_port>; | ||
171 | }; | ||
172 | }; | ||
173 | |||
174 | }; | ||
175 | }; | ||
176 | |||
177 | 3. Sources | ||
178 | ptm@2201c000 { | ||
179 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
180 | reg = <0 0x2201c000 0 0x1000>; | ||
181 | |||
182 | cpu = <&cpu0>; | ||
183 | clocks = <&oscclk6a>; | ||
184 | clock-names = "apb_pclk"; | ||
185 | port { | ||
186 | ptm0_out_port: endpoint { | ||
187 | remote-endpoint = <&funnel_in_port0>; | ||
188 | }; | ||
189 | }; | ||
190 | }; | ||
191 | |||
192 | ptm@2201d000 { | ||
193 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
194 | reg = <0 0x2201d000 0 0x1000>; | ||
195 | |||
196 | cpu = <&cpu1>; | ||
197 | clocks = <&oscclk6a>; | ||
198 | clock-names = "apb_pclk"; | ||
199 | port { | ||
200 | ptm1_out_port: endpoint { | ||
201 | remote-endpoint = <&funnel_in_port1>; | ||
202 | }; | ||
203 | }; | ||
204 | }; | ||