diff options
author | Chanwoo Choi <cw00.choi@samsung.com> | 2015-02-02 19:13:52 -0500 |
---|---|---|
committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-02-05 13:31:05 -0500 |
commit | 9910b6bbaa7b16cd3a8a7d8be53980fa1b8183a6 (patch) | |
tree | 294a23f01e73f9c983b9fc536b40d74ed671efcd /Documentation | |
parent | b274bbfd8b4a94cb5bd6fe21801264a27dd8ec75 (diff) |
clk: samsung: exynos5433: Add clocks for CMU_MFC domain
This patch adds the mux/divider/gate clocks for CMU_MFC domain which
generates the clocks for MFC(Multi-Format Codec) IP.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/clock/exynos5433-clock.txt | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index ecb9534c2ea6..0f35167ec15c 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt | |||
@@ -39,6 +39,8 @@ Required Properties: | |||
39 | L2 cache controller. | 39 | L2 cache controller. |
40 | - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL | 40 | - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL |
41 | which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. | 41 | which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. |
42 | - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC | ||
43 | which generates clocks for MFC(Multi-Format Codec) IP. | ||
42 | 44 | ||
43 | - reg: physical base address of the controller and length of memory mapped | 45 | - reg: physical base address of the controller and length of memory mapped |
44 | region. | 46 | region. |
@@ -125,6 +127,10 @@ Required Properties: | |||
125 | - sclk_jpeg_mscl | 127 | - sclk_jpeg_mscl |
126 | - aclk_mscl_400 | 128 | - aclk_mscl_400 |
127 | 129 | ||
130 | Input clocks for mfc clock controller: | ||
131 | - oscclk | ||
132 | - aclk_mfc_400 | ||
133 | |||
128 | Each clock is assigned an identifier and client nodes can use this identifier | 134 | Each clock is assigned an identifier and client nodes can use this identifier |
129 | to specify the clock which they consume. | 135 | to specify the clock which they consume. |
130 | 136 | ||
@@ -340,6 +346,15 @@ Example 2: Examples of clock controller nodes are listed below. | |||
340 | <&cmu_top CLK_ACLK_MSCL_400>; | 346 | <&cmu_top CLK_ACLK_MSCL_400>; |
341 | }; | 347 | }; |
342 | 348 | ||
349 | cmu_mfc: clock-controller@15280000 { | ||
350 | compatible = "samsung,exynos5433-cmu-mfc"; | ||
351 | reg = <0x15280000 0x0b08>; | ||
352 | #clock-cells = <1>; | ||
353 | |||
354 | clock-names = "oscclk", "aclk_mfc_400"; | ||
355 | clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; | ||
356 | }; | ||
357 | |||
343 | Example 3: UART controller node that consumes the clock generated by the clock | 358 | Example 3: UART controller node that consumes the clock generated by the clock |
344 | controller. | 359 | controller. |
345 | 360 | ||