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authorOlof Johansson <olof@lixom.net>2013-04-11 06:38:03 -0400
committerOlof Johansson <olof@lixom.net>2013-04-11 06:38:03 -0400
commit83c15f4c05757b3c5fe1551a474458fd16d27bae (patch)
treec9631bf611794e15a0afc3fb0673e7e494ca94d0 /Documentation
parentd6e911b599517d3faaa53e125b174a318b33aca9 (diff)
parent918d7f6f68620e0721bb31402ebf87e15f826831 (diff)
Merge branch 'depends/clk-for-3.10' into next/cleanup
Bringin in clk subsystem dependencies needed by sunxi. * depends/clk-for-3.10: (26 commits) clk: sunxi: drop an unnecesary kmalloc clk: sunxi: drop CLK_IGNORE_UNUSED clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag clk: mvebu: Use common of_clk_init() function clk: fix clk_mux::flags kerneldoc clk: allow reentrant calls into the clk framework clk: abstract locking out into helper functions clk: zynq: Add missing zynq clk header clk: sunxi: rename compatible strings arm: sunxi: Add useful information about sunxi clocks clk: arm: sunxi: Add a new clock driver for sunxi SOCs clk: ux500: Fix prcmu clocks registration ARM: imx: adapt clk_busy_mux to new clk_mux struct clk: Add composite clock type clk: add table lookup to mux clk: Fix incorrect return type in clk.c clk: prima2: fix return value check in sirfsoc_of_clk_init() clk:SPEAr1340: Correct parent clock configuration documentation: clk: fix couple of misspelling ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/arm/sunxi/clocks.txt56
-rw-r--r--Documentation/clk.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/axi-clkgen.txt22
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt151
4 files changed, 231 insertions, 2 deletions
diff --git a/Documentation/arm/sunxi/clocks.txt b/Documentation/arm/sunxi/clocks.txt
new file mode 100644
index 000000000000..e09a88aa3136
--- /dev/null
+++ b/Documentation/arm/sunxi/clocks.txt
@@ -0,0 +1,56 @@
1Frequently asked questions about the sunxi clock system
2=======================================================
3
4This document contains useful bits of information that people tend to ask
5about the sunxi clock system, as well as accompanying ASCII art when adequate.
6
7Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
8 system?
9
10A: The 24MHz oscillator allows gating to save power. Indeed, if gated
11 carelessly the system would stop functioning, but with the right
12 steps, one can gate it and keep the system running. Consider this
13 simplified suspend example:
14
15 While the system is operational, you would see something like
16
17 24MHz 32kHz
18 |
19 PLL1
20 \
21 \_ CPU Mux
22 |
23 [CPU]
24
25 When you are about to suspend, you switch the CPU Mux to the 32kHz
26 oscillator:
27
28 24Mhz 32kHz
29 | |
30 PLL1 |
31 /
32 CPU Mux _/
33 |
34 [CPU]
35
36 Finally you can gate the main oscillator
37
38 32kHz
39 |
40 |
41 /
42 CPU Mux _/
43 |
44 [CPU]
45
46Q: Were can I learn more about the sunxi clocks?
47
48A: The linux-sunxi wiki contains a page documenting the clock registers,
49 you can find it at
50
51 http://linux-sunxi.org/A10/CCM
52
53 The authoritative source for information at this time is the ccmu driver
54 released by Allwinner, you can find it at
55
56 https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 1943fae014fd..4274a546eb57 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
174}; 174};
175 175
176Below is a matrix detailing which clk_ops are mandatory based upon the 176Below is a matrix detailing which clk_ops are mandatory based upon the
177hardware capbilities of that clock. A cell marked as "y" means 177hardware capabilities of that clock. A cell marked as "y" means
178mandatory, a cell marked as "n" implies that either including that 178mandatory, a cell marked as "n" implies that either including that
179callback is invalid or otherwise uneccesary. Empty cells are either 179callback is invalid or otherwise unnecessary. Empty cells are either
180optional or must be evaluated on a case-by-case basis. 180optional or must be evaluated on a case-by-case basis.
181 181
182 clock hardware characteristics 182 clock hardware characteristics
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
new file mode 100644
index 000000000000..028b493e97ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -0,0 +1,22 @@
1Binding for the axi-clkgen clock generator
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be "adi,axi-clkgen".
9- #clock-cells : from common clock binding; Should always be set to 0.
10- reg : Address and length of the axi-clkgen register set.
11- clocks : Phandle and clock specifier for the parent clock.
12
13Optional properties:
14- clock-output-names : From common clock binding.
15
16Example:
17 clock@0xff000000 {
18 compatible = "adi,axi-clkgen";
19 #clock-cells = <0>;
20 reg = <0xff000000 0x1000>;
21 clocks = <&osc 1>;
22 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 000000000000..729f52426fe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,151 @@
1Device Tree Clock bindings for arch-sunxi
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
14 "allwinner,sun4i-ahb-clk" - for the AHB clock
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
16 "allwinner,sun4i-apb0-clk" - for the APB0 clock
17 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
18 "allwinner,sun4i-apb1-clk" - for the APB1 clock
19 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
20 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
21
22Required properties for all clocks:
23- reg : shall be the control register address for the clock.
24- clocks : shall be the input parent clock(s) phandle for the clock
25- #clock-cells : from common clock binding; shall be set to 0 except for
26 "allwinner,sun4i-*-gates-clk" where it shall be set to 1
27
28Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
29- clock-output-names : the corresponding gate names that the clock controls
30
31For example:
32
33osc24M: osc24M@01c20050 {
34 #clock-cells = <0>;
35 compatible = "allwinner,sun4i-osc-clk";
36 reg = <0x01c20050 0x4>;
37 clocks = <&osc24M_fixed>;
38};
39
40pll1: pll1@01c20000 {
41 #clock-cells = <0>;
42 compatible = "allwinner,sun4i-pll1-clk";
43 reg = <0x01c20000 0x4>;
44 clocks = <&osc24M>;
45};
46
47cpu: cpu@01c20054 {
48 #clock-cells = <0>;
49 compatible = "allwinner,sun4i-cpu-clk";
50 reg = <0x01c20054 0x4>;
51 clocks = <&osc32k>, <&osc24M>, <&pll1>;
52};
53
54
55
56Gate clock outputs
57
58The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
59their corresponding offsets as present on sun4i are listed below. Note that
60some of these gates are not present on sun5i.
61
62 * AXI gates ("allwinner,sun4i-axi-gates-clk")
63
64 DRAM 0
65
66 * AHB gates ("allwinner,sun4i-ahb-gates-clk")
67
68 USB0 0
69 EHCI0 1
70 OHCI0 2*
71 EHCI1 3
72 OHCI1 4*
73 SS 5
74 DMA 6
75 BIST 7
76 MMC0 8
77 MMC1 9
78 MMC2 10
79 MMC3 11
80 MS 12**
81 NAND 13
82 SDRAM 14
83
84 ACE 16
85 EMAC 17
86 TS 18
87
88 SPI0 20
89 SPI1 21
90 SPI2 22
91 SPI3 23
92 PATA 24
93 SATA 25**
94 GPS 26*
95
96 VE 32
97 TVD 33
98 TVE0 34
99 TVE1 35
100 LCD0 36
101 LCD1 37
102
103 CSI0 40
104 CSI1 41
105
106 HDMI 43
107 DE_BE0 44
108 DE_BE1 45
109 DE_FE0 46
110 DE_FE1 47
111
112 MP 50
113
114 MALI400 52
115
116 * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
117
118 CODEC 0
119 SPDIF 1*
120 AC97 2
121 IIS 3
122
123 PIO 5
124 IR0 6
125 IR1 7
126
127 KEYPAD 10
128
129 * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
130
131 I2C0 0
132 I2C1 1
133 I2C2 2
134
135 CAN 4
136 SCR 5
137 PS20 6
138 PS21 7
139
140 UART0 16
141 UART1 17
142 UART2 18
143 UART3 19
144 UART4 20
145 UART5 21
146 UART6 22
147 UART7 23
148
149Notation:
150 [*]: The datasheet didn't mention these, but they are present on AW code
151 [**]: The datasheet had this marked as "NC" but they are used on AW code
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 03:11:57 -0400