Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:
 "For dmaengine contributions we have:
   - designware cleanup by Andy
   - my series moving device_control users to dmanegine_xxx APIs for
     later removal of device_control API
   - minor fixes spread over drivers mainly mv_xor, pl330, mmp, imx-sdma
     etc"

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (60 commits)
  serial: atmel: add missing dmaengine header
  dmaengine: remove FSLDMA_EXTERNAL_START
  dmaengine: freescale: remove FSLDMA_EXTERNAL_START control method
  carma-fpga: move to fsl_dma_external_start()
  carma-fpga: use dmaengine_xxx() API
  dmaengine: freescale: add and export fsl_dma_external_start()
  dmaengine: add dmaengine_prep_dma_sg() helper
  video: mx3fb: use dmaengine_terminate_all() API
  serial: sh-sci: use dmaengine_terminate_all() API
  net: ks8842: use dmaengine_terminate_all() API
  mtd: sh_flctl: use dmaengine_terminate_all() API
  mtd: fsmc_nand: use dmaengine_terminate_all() API
  V4L2: mx3_camer: use dmaengine_pause() API
  dmaengine: coh901318: use dmaengine_terminate_all() API
  pata_arasan_cf: use dmaengine_terminate_all() API
  dmaengine: edma: check for echan->edesc => NULL in edma_dma_pause()
  dmaengine: dw: export probe()/remove() and Co to users
  dmaengine: dw: enable and disable controller when needed
  dmaengine: dw: always export dw_dma_{en,dis}able
  dmaengine: dw: introduce dw_dma_on() helper
  ...

3 files changed, 129 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt
new file mode 100644
index 000000000000..9bcab9115982
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -0,0 +1,62 @@
+QCOM ADM DMA Controller
+
+Required properties:
+- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
+- reg: Address range for DMA registers
+- interrupts: Should contain one interrupt shared by all channels
+- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell
+  denotes CRCI (client rate control interface) flow control assignment.
+- clocks: Should contain the core clock and interface clock.
+- clock-names: Must contain "core" for the core clock and "iface" for the
+  interface clock.
+- resets: Must contain an entry for each entry in reset names.
+- reset-names: Must include the following entries:
+  - clk
+  - c0
+  - c1
+  - c2
+- qcom,ee: indicates the security domain identifier used in the secure world.
+
+Example:
+                adm_dma: dma@18300000 {
+                        compatible = "qcom,adm";
+                        reg = <0x18300000 0x100000>;
+                        interrupts = <0 170 0>;
+                        #dma-cells = <2>;
+
+                        clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+                        clock-names = "core", "iface";
+
+                        resets = <&gcc ADM0_RESET>,
+                                <&gcc ADM0_C0_RESET>,
+                                <&gcc ADM0_C1_RESET>,
+                                <&gcc ADM0_C2_RESET>;
+                        reset-names = "clk", "c0", "c1", "c2";
+                        qcom,ee = <0>;
+                };
+
+DMA clients must use the format descripted in the dma.txt file, using a three
+cell specifier for each channel.
+
+Each dmas request consists of 3 cells:
+ 1. phandle pointing to the DMA controller
+ 2. channel number
+ 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.
+    The CRCI is used for flow control.  It identifies the peripheral device that
+    is the source/destination for the transferred data.
+
+Example:
+
+        spi4: spi@1a280000 {
+                status = "ok";
+                spi-max-frequency = <50000000>;
+
+                pinctrl-0 = <&spi_pins>;
+                pinctrl-names = "default";
+
+                cs-gpios = <&qcom_pinmux 20 0>;
+
+                dmas = <&adm_dma 6 9>,
+                        <&adm_dma 5 10>;
+                dma-names = "rx", "tx";
+        };
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
new file mode 100644
index 000000000000..2291c4098730
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -0,0 +1,65 @@
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Required properties:
+- compatible: Should be "xlnx,axi-dma-1.00.a"
+- #dma-cells: Should be <1>, see "dmas" property below
+- reg: Should contain DMA registers location and length.
+- dma-channel child node: Should have atleast one channel and can have upto
+        two channels per device. This node specifies the properties of each
+        DMA channel (see child node properties below).
+
+Optional properties:
+- xlnx,include-sg: Tells whether configured for Scatter-mode in
+        the hardware.
+
+Required child node properties:
+- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
+        "xlnx,axi-dma-s2mm-channel".
+- interrupts: Should contain per channel DMA interrupts.
+- xlnx,datawidth: Should contain the stream data width, take values
+        {32,64...1024}.
+
+Option child node properties:
+- xlnx,include-dre: Tells whether hardware is configured for Data
+        Realignment Engine.
+
+Example:
+++++++++
+
+axi_dma_0: axidma@40400000 {
+        compatible = "xlnx,axi-dma-1.00.a";
+        #dma_cells = <1>;
+        reg = < 0x40400000 0x10000 >;
+        dma-channel@40400000 {
+                compatible = "xlnx,axi-dma-mm2s-channel";
+                interrupts = < 0 59 4 >;
+                xlnx,datawidth = <0x40>;
+        } ;
+        dma-channel@40400030 {
+                compatible = "xlnx,axi-dma-s2mm-channel";
+                interrupts = < 0 58 4 >;
+                xlnx,datawidth = <0x40>;
+        } ;
+} ;
+
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
+        where Channel ID is '0' for write/tx and '1' for read/rx
+        channel.
+- dma-names: a list of DMA channel names, one per "dmas" entry
+
+Example:
+++++++++
+
+dmatest_0: dmatest@0 {
+        compatible ="xlnx,axi-dma-test-1.00.a";
+        dmas = <&axi_dma_0 0
+                &axi_dma_0 1>;
+        dma-names = "dma0", "dma1";
+} ;
diff --git a/Documentation/dmaengine.txt b/Documentation/dmaengine.txt
index 573e28ce9751..11fb87ff6cd0 100644
--- a/Documentation/dmaengine.txt
+++ b/Documentation/dmaengine.txt
@@ -98,7 +98,7 @@ The slave DMA usage consists of following steps:
                 unsigned long flags);
 
    The peripheral driver is expected to have mapped the scatterlist for
-   the DMA operation prior to calling device_prep_slave_sg, and must
+   the DMA operation prior to calling dmaengine_prep_slave_sg(), and must
    keep the scatterlist mapped until the DMA operation has completed.
    The scatterlist must be mapped using the DMA struct device.
    If a mapping needs to be synchronized later, dma_sync_*_for_*() must be
@@ -195,5 +195,5 @@ Further APIs:
    Note:
         Not all DMA engine drivers can return reliable information for
         a running DMA channel.  It is recommended that DMA engine users
-        pause or stop (via dmaengine_terminate_all) the channel before
+        pause or stop (via dmaengine_terminate_all()) the channel before
         using this API.