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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-04-30 05:56:22 -0400
committerMike Turquette <mturquette@linaro.org>2013-05-29 01:50:31 -0400
commit4f985b4c800e824cd4fdde00c9575dd573a7b933 (patch)
treec9e4cf481e95a7e8b1de074fc05ac9f713ad88b0 /Documentation
parent20faa59e0f3e3e6a6afeeaa7d976debacfce4fe3 (diff)
clk: sun5i: Add compatibles for Allwinner A13
The A13 has a lot less clocks than the one found in the Allwinner A10. Add these stripped down clocks to the clock driver and in the documentation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt117
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt93
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt58
3 files changed, 164 insertions, 104 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 729f52426fe1..d495521a79d2 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -12,22 +12,30 @@ Required properties:
12 "allwinner,sun4i-axi-clk" - for the AXI clock 12 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates 13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
14 "allwinner,sun4i-ahb-clk" - for the AHB clock 14 "allwinner,sun4i-ahb-clk" - for the AHB clock
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates 15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
16 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
16 "allwinner,sun4i-apb0-clk" - for the APB0 clock 17 "allwinner,sun4i-apb0-clk" - for the APB0 clock
17 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates 18 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
19 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
18 "allwinner,sun4i-apb1-clk" - for the APB1 clock 20 "allwinner,sun4i-apb1-clk" - for the APB1 clock
19 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing 21 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
20 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates 22 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
23 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
21 24
22Required properties for all clocks: 25Required properties for all clocks:
23- reg : shall be the control register address for the clock. 26- reg : shall be the control register address for the clock.
24- clocks : shall be the input parent clock(s) phandle for the clock 27- clocks : shall be the input parent clock(s) phandle for the clock
25- #clock-cells : from common clock binding; shall be set to 0 except for 28- #clock-cells : from common clock binding; shall be set to 0 except for
26 "allwinner,sun4i-*-gates-clk" where it shall be set to 1 29 "allwinner,*-gates-clk" where it shall be set to 1
27 30
28Additionally, "allwinner,sun4i-*-gates-clk" clocks require: 31Additionally, "allwinner,*-gates-clk" clocks require:
29- clock-output-names : the corresponding gate names that the clock controls 32- clock-output-names : the corresponding gate names that the clock controls
30 33
34Clock consumers should specify the desired clocks they use with a
35"clocks" phandle cell. Consumers that are using a gated clock should
36provide an additional ID in their clock property. The values of this
37ID are documented in sunxi/<soc>-gates.txt.
38
31For example: 39For example:
32 40
33osc24M: osc24M@01c20050 { 41osc24M: osc24M@01c20050 {
@@ -50,102 +58,3 @@ cpu: cpu@01c20054 {
50 reg = <0x01c20054 0x4>; 58 reg = <0x01c20054 0x4>;
51 clocks = <&osc32k>, <&osc24M>, <&pll1>; 59 clocks = <&osc32k>, <&osc24M>, <&pll1>;
52}; 60};
53
54
55
56Gate clock outputs
57
58The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
59their corresponding offsets as present on sun4i are listed below. Note that
60some of these gates are not present on sun5i.
61
62 * AXI gates ("allwinner,sun4i-axi-gates-clk")
63
64 DRAM 0
65
66 * AHB gates ("allwinner,sun4i-ahb-gates-clk")
67
68 USB0 0
69 EHCI0 1
70 OHCI0 2*
71 EHCI1 3
72 OHCI1 4*
73 SS 5
74 DMA 6
75 BIST 7
76 MMC0 8
77 MMC1 9
78 MMC2 10
79 MMC3 11
80 MS 12**
81 NAND 13
82 SDRAM 14
83
84 ACE 16
85 EMAC 17
86 TS 18
87
88 SPI0 20
89 SPI1 21
90 SPI2 22
91 SPI3 23
92 PATA 24
93 SATA 25**
94 GPS 26*
95
96 VE 32
97 TVD 33
98 TVE0 34
99 TVE1 35
100 LCD0 36
101 LCD1 37
102
103 CSI0 40
104 CSI1 41
105
106 HDMI 43
107 DE_BE0 44
108 DE_BE1 45
109 DE_FE0 46
110 DE_FE1 47
111
112 MP 50
113
114 MALI400 52
115
116 * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
117
118 CODEC 0
119 SPDIF 1*
120 AC97 2
121 IIS 3
122
123 PIO 5
124 IR0 6
125 IR1 7
126
127 KEYPAD 10
128
129 * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
130
131 I2C0 0
132 I2C1 1
133 I2C2 2
134
135 CAN 4
136 SCR 5
137 PS20 6
138 PS21 7
139
140 UART0 16
141 UART1 17
142 UART2 18
143 UART3 19
144 UART4 20
145 UART5 21
146 UART6 22
147 UART7 23
148
149Notation:
150 [*]: The datasheet didn't mention these, but they are present on AW code
151 [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
new file mode 100644
index 000000000000..6a03475bbfe2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
@@ -0,0 +1,93 @@
1Gate clock outputs
2------------------
3
4 * AXI gates ("allwinner,sun4i-axi-gates-clk")
5
6 DRAM 0
7
8 * AHB gates ("allwinner,sun4i-ahb-gates-clk")
9
10 USB0 0
11 EHCI0 1
12 OHCI0 2*
13 EHCI1 3
14 OHCI1 4*
15 SS 5
16 DMA 6
17 BIST 7
18 MMC0 8
19 MMC1 9
20 MMC2 10
21 MMC3 11
22 MS 12**
23 NAND 13
24 SDRAM 14
25
26 ACE 16
27 EMAC 17
28 TS 18
29
30 SPI0 20
31 SPI1 21
32 SPI2 22
33 SPI3 23
34 PATA 24
35 SATA 25**
36 GPS 26*
37
38 VE 32
39 TVD 33
40 TVE0 34
41 TVE1 35
42 LCD0 36
43 LCD1 37
44
45 CSI0 40
46 CSI1 41
47
48 HDMI 43
49 DE_BE0 44
50 DE_BE1 45
51 DE_FE1 46
52 DE_FE1 47
53
54 MP 50
55
56 MALI400 52
57
58 * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
59
60 CODEC 0
61 SPDIF 1*
62 AC97 2
63 IIS 3
64
65 PIO 5
66 IR0 6
67 IR1 7
68
69 KEYPAD 10
70
71 * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
72
73 I2C0 0
74 I2C1 1
75 I2C2 2
76
77 CAN 4
78 SCR 5
79 PS20 6
80 PS21 7
81
82 UART0 16
83 UART1 17
84 UART2 18
85 UART3 19
86 UART4 20
87 UART5 21
88 UART6 22
89 UART7 23
90
91Notation:
92 [*]: The datasheet didn't mention these, but they are present on AW code
93 [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
new file mode 100644
index 000000000000..006b6dfc4703
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
@@ -0,0 +1,58 @@
1Gate clock outputs
2------------------
3
4 * AXI gates ("allwinner,sun4i-axi-gates-clk")
5
6 DRAM 0
7
8 * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
9
10 USBOTG 0
11 EHCI 1
12 OHCI 2
13
14 SS 5
15 DMA 6
16 BIST 7
17 MMC0 8
18 MMC1 9
19 MMC2 10
20
21 NAND 13
22 SDRAM 14
23
24 SPI0 20
25 SPI1 21
26 SPI2 22
27
28 STIMER 28
29
30 VE 32
31
32 LCD 36
33
34 CSI 40
35
36 DE_BE 44
37
38 DE_FE 46
39
40 IEP 51
41 MALI400 52
42
43 * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
44
45 CODEC 0
46
47 PIO 5
48 IR 6
49
50 * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
51
52 I2C0 0
53 I2C1 1
54 I2C2 2
55
56 UART1 17
57
58 UART3 19
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 03:46:01 -0500