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authorAlexander Shiyan <shc_work@mail.ru>2013-06-29 00:27:54 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-08-16 00:59:44 -0400
commit3f98b6baad63b181da4e859d81953e88ce8a50ec (patch)
tree6e6c227c95f3955044558dbe9d65da3beb1edb80 /Documentation
parentfc608c745cf71a7abb673d891104597120042f21 (diff)
drivers: bus: imx-weim: Add support for i.MX1/21/25/27/31/35/50/51/53
This patch adds WEIM support for all i.MX CPUs supported by the kernel. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/bus/imx-weim.txt17
1 files changed, 12 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
index cedc2a9c4785..0fd76c405208 100644
--- a/Documentation/devicetree/bindings/bus/imx-weim.txt
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -8,7 +8,7 @@ The actual devices are instantiated from the child nodes of a WEIM node.
8 8
9Required properties: 9Required properties:
10 10
11 - compatible: Should be set to "fsl,imx6q-weim" 11 - compatible: Should be set to "fsl,<soc>-weim"
12 - reg: A resource specifier for the register space 12 - reg: A resource specifier for the register space
13 (see the example below) 13 (see the example below)
14 - clocks: the clock, see the example below. 14 - clocks: the clock, see the example below.
@@ -21,11 +21,18 @@ Required properties:
21 21
22Timing property for child nodes. It is mandatory, not optional. 22Timing property for child nodes. It is mandatory, not optional.
23 23
24 - fsl,weim-cs-timing: The timing array, contains 6 timing values for the 24 - fsl,weim-cs-timing: The timing array, contains timing values for the
25 child node. We can get the CS index from the child 25 child node. We can get the CS index from the child
26 node's "reg" property. This property contains the values 26 node's "reg" property. The number of registers depends
27 for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1, 27 on the selected chip.
28 EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order. 28 For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
29 registers: CSxU, CSxL.
30 For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
31 there are three registers: CSCRxU, CSCRxL, CSCRxA.
32 For i.MX50, i.MX53 ("fsl,imx50-weim"),
33 i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
34 there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
35 CSxRCR2, CSxWCR1, CSxWCR2.
29 36
30Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: 37Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
31 38