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authorArnd Bergmann <arnd@arndb.de>2013-04-09 16:24:06 -0400
committerArnd Bergmann <arnd@arndb.de>2013-04-09 16:28:45 -0400
commit19ce4f4a03e52bc694dc837a4a832111cb4271b3 (patch)
tree79757bb645e035166ca012373992e185f8d07081 /Documentation
parent228e3023eb0430b4b9ed0736f8f87c96a6cd9c7a (diff)
parentda821eb7d42935b0f7056d98c75fd1150f6636f4 (diff)
Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>: add suppport common clock framework for exynos * tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits) ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: exynos5250: register display block gate clocks to common clock framework clk: exynos4: Add support for SoC-specific register save list clk: exynos4: Add missing registers to suspend save list clk: exynos4: Remove E4X12 prefix from SRC_DMC register clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register clk: exynos4: Add E4210 prefix to LCD1 clock registers clk: exynos4: Remove SoC-specific registers from save list clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions clk: exynos4: Define {E,V}PLL registers clk: exynos4: Add missing mout_sata on Exynos4210 clk: exynos4: Add missing CMU_TOP and ISP clocks clk: exynos4: Add G3D clocks clk: exynos4: Add camera related clock definitions clk: exynos4: Export mout_core clock of Exynos4210 clk: samsung: Remove unimplemented ops for pll clk: exynos4: Export clocks used by exynos cpufreq drivers ... [arnd: add missing #address-cells property in mshc DT node] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt288
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt177
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5440-clock.txt61
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt21
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt40
5 files changed, 587 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 000000000000..ea5e26f16aec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,288 @@
1* Samsung Exynos4 Clock Controller
2
3The Exynos4 clock controller generates and supplies clock to various controllers
4within the Exynos4 SoC. The clock binding described here is applicable to all
5SoC's in the Exynos4 family.
6
7Required Properties:
8
9- comptible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12
13- reg: physical base address of the controller and length of memory mapped
14 region.
15
16- #clock-cells: should be 1.
17
18The following is the list of clocks generated by the controller. Each clock is
19assigned an identifier and client nodes use this identifier to specify the
20clock which they consume. Some of the clocks are available only on a particular
21Exynos4 SoC and this is specified where applicable.
22
23
24 [Core Clocks]
25
26 Clock ID SoC (if specific)
27 -----------------------------------------------
28
29 xxti 1
30 xusbxti 2
31 fin_pll 3
32 fout_apll 4
33 fout_mpll 5
34 fout_epll 6
35 fout_vpll 7
36 sclk_apll 8
37 sclk_mpll 9
38 sclk_epll 10
39 sclk_vpll 11
40 arm_clk 12
41 aclk200 13
42 aclk100 14
43 aclk160 15
44 aclk133 16
45 mout_mpll_user_t 17 Exynos4x12
46 mout_mpll_user_c 18 Exynos4x12
47 mout_core 19
48 mout_apll 20
49
50
51 [Clock Gate for Special Clocks]
52
53 Clock ID SoC (if specific)
54 -----------------------------------------------
55
56 sclk_fimc0 128
57 sclk_fimc1 129
58 sclk_fimc2 130
59 sclk_fimc3 131
60 sclk_cam0 132
61 sclk_cam1 133
62 sclk_csis0 134
63 sclk_csis1 135
64 sclk_hdmi 136
65 sclk_mixer 137
66 sclk_dac 138
67 sclk_pixel 139
68 sclk_fimd0 140
69 sclk_mdnie0 141 Exynos4412
70 sclk_mdnie_pwm0 12 142 Exynos4412
71 sclk_mipi0 143
72 sclk_audio0 144
73 sclk_mmc0 145
74 sclk_mmc1 146
75 sclk_mmc2 147
76 sclk_mmc3 148
77 sclk_mmc4 149
78 sclk_sata 150 Exynos4210
79 sclk_uart0 151
80 sclk_uart1 152
81 sclk_uart2 153
82 sclk_uart3 154
83 sclk_uart4 155
84 sclk_audio1 156
85 sclk_audio2 157
86 sclk_spdif 158
87 sclk_spi0 159
88 sclk_spi1 160
89 sclk_spi2 161
90 sclk_slimbus 162
91 sclk_fimd1 163 Exynos4210
92 sclk_mipi1 164 Exynos4210
93 sclk_pcm1 165
94 sclk_pcm2 166
95 sclk_i2s1 167
96 sclk_i2s2 168
97 sclk_mipihsi 169 Exynos4412
98 sclk_mfc 170
99 sclk_pcm0 171
100 sclk_g3d 172
101 sclk_pwm_isp 173 Exynos4x12
102 sclk_spi0_isp 174 Exynos4x12
103 sclk_spi1_isp 175 Exynos4x12
104 sclk_uart_isp 176 Exynos4x12
105
106 [Peripheral Clock Gates]
107
108 Clock ID SoC (if specific)
109 -----------------------------------------------
110
111 fimc0 256
112 fimc1 257
113 fimc2 258
114 fimc3 259
115 csis0 260
116 csis1 261
117 jpeg 262
118 smmu_fimc0 263
119 smmu_fimc1 264
120 smmu_fimc2 265
121 smmu_fimc3 266
122 smmu_jpeg 267
123 vp 268
124 mixer 269
125 tvenc 270 Exynos4210
126 hdmi 271
127 smmu_tv 272
128 mfc 273
129 smmu_mfcl 274
130 smmu_mfcr 275
131 g3d 276
132 g2d 277 Exynos4210
133 rotator 278 Exynos4210
134 mdma 279 Exynos4210
135 smmu_g2d 280 Exynos4210
136 smmu_rotator 281 Exynos4210
137 smmu_mdma 282 Exynos4210
138 fimd0 283
139 mie0 284
140 mdnie0 285 Exynos4412
141 dsim0 286
142 smmu_fimd0 287
143 fimd1 288 Exynos4210
144 mie1 289 Exynos4210
145 dsim1 290 Exynos4210
146 smmu_fimd1 291 Exynos4210
147 pdma0 292
148 pdma1 293
149 pcie_phy 294
150 sata_phy 295 Exynos4210
151 tsi 296
152 sdmmc0 297
153 sdmmc1 298
154 sdmmc2 299
155 sdmmc3 300
156 sdmmc4 301
157 sata 302 Exynos4210
158 sromc 303
159 usb_host 304
160 usb_device 305
161 pcie 306
162 onenand 307
163 nfcon 308
164 smmu_pcie 309
165 gps 310
166 smmu_gps 311
167 uart0 312
168 uart1 313
169 uart2 314
170 uart3 315
171 uart4 316
172 i2c0 317
173 i2c1 318
174 i2c2 319
175 i2c3 320
176 i2c4 321
177 i2c5 322
178 i2c6 323
179 i2c7 324
180 i2c_hdmi 325
181 tsadc 326
182 spi0 327
183 spi1 328
184 spi2 329
185 i2s1 330
186 i2s2 331
187 pcm0 332
188 i2s0 333
189 pcm1 334
190 pcm2 335
191 pwm 336
192 slimbus 337
193 spdif 338
194 ac97 339
195 modemif 340
196 chipid 341
197 sysreg 342
198 hdmi_cec 343
199 mct 344
200 wdt 345
201 rtc 346
202 keyif 347
203 audss 348
204 mipi_hsi 349 Exynos4210
205 mdma2 350 Exynos4210
206 pixelasyncm0 351
207 pixelasyncm1 352
208 fimc_lite0 353 Exynos4x12
209 fimc_lite1 354 Exynos4x12
210 ppmuispx 355 Exynos4x12
211 ppmuispmx 356 Exynos4x12
212 fimc_isp 357 Exynos4x12
213 fimc_drc 358 Exynos4x12
214 fimc_fd 359 Exynos4x12
215 mcuisp 360 Exynos4x12
216 gicisp 361 Exynos4x12
217 smmu_isp 362 Exynos4x12
218 smmu_drc 363 Exynos4x12
219 smmu_fd 364 Exynos4x12
220 smmu_lite0 365 Exynos4x12
221 smmu_lite1 366 Exynos4x12
222 mcuctl_isp 367 Exynos4x12
223 mpwm_isp 368 Exynos4x12
224 i2c0_isp 369 Exynos4x12
225 i2c1_isp 370 Exynos4x12
226 mtcadc_isp 371 Exynos4x12
227 pwm_isp 372 Exynos4x12
228 wdt_isp 373 Exynos4x12
229 uart_isp 374 Exynos4x12
230 asyncaxim 375 Exynos4x12
231 smmu_ispcx 376 Exynos4x12
232 spi0_isp 377 Exynos4x12
233 spi1_isp 378 Exynos4x12
234 pwm_isp_sclk 379 Exynos4x12
235 spi0_isp_sclk 380 Exynos4x12
236 spi1_isp_sclk 381 Exynos4x12
237 uart_isp_sclk 382 Exynos4x12
238
239 [Mux Clocks]
240
241 Clock ID SoC (if specific)
242 -----------------------------------------------
243
244 mout_fimc0 384
245 mout_fimc1 385
246 mout_fimc2 386
247 mout_fimc3 387
248 mout_cam0 388
249 mout_cam1 389
250 mout_csis0 390
251 mout_csis1 391
252 mout_g3d0 392
253 mout_g3d1 393
254 mout_g3d 394
255 aclk400_mcuisp 395 Exynos4x12
256
257 [Div Clocks]
258
259 Clock ID SoC (if specific)
260 -----------------------------------------------
261
262 div_isp0 450 Exynos4x12
263 div_isp1 451 Exynos4x12
264 div_mcuisp0 452 Exynos4x12
265 div_mcuisp1 453 Exynos4x12
266 div_aclk200 454 Exynos4x12
267 div_aclk400_mcuisp 455 Exynos4x12
268
269
270Example 1: An example of a clock controller node is listed below.
271
272 clock: clock-controller@0x10030000 {
273 compatible = "samsung,exynos4210-clock";
274 reg = <0x10030000 0x20000>;
275 #clock-cells = <1>;
276 };
277
278Example 2: UART controller node that consumes the clock generated by the clock
279 controller. Refer to the standard clock bindings for information
280 about 'clocks' and 'clock-names' property.
281
282 serial@13820000 {
283 compatible = "samsung,exynos4210-uart";
284 reg = <0x13820000 0x100>;
285 interrupts = <0 54 0>;
286 clocks = <&clock 314>, <&clock 153>;
287 clock-names = "uart", "clk_uart_baud0";
288 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 000000000000..781a6276adf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,177 @@
1* Samsung Exynos5250 Clock Controller
2
3The Exynos5250 clock controller generates and supplies clock to various
4controllers within the Exynos5250 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32
33 sclk_cam_bayer 128
34 sclk_cam0 129
35 sclk_cam1 130
36 sclk_gscl_wa 131
37 sclk_gscl_wb 132
38 sclk_fimd1 133
39 sclk_mipi1 134
40 sclk_dp 135
41 sclk_hdmi 136
42 sclk_pixel 137
43 sclk_audio0 138
44 sclk_mmc0 139
45 sclk_mmc1 140
46 sclk_mmc2 141
47 sclk_mmc3 142
48 sclk_sata 143
49 sclk_usb3 144
50 sclk_jpeg 145
51 sclk_uart0 146
52 sclk_uart1 147
53 sclk_uart2 148
54 sclk_uart3 149
55 sclk_pwm 150
56 sclk_audio1 151
57 sclk_audio2 152
58 sclk_spdif 153
59 sclk_spi0 154
60 sclk_spi1 155
61 sclk_spi2 156
62
63
64 [Peripheral Clock Gates]
65
66 Clock ID
67 ----------------------------
68
69 gscl0 256
70 gscl1 257
71 gscl2 258
72 gscl3 259
73 gscl_wa 260
74 gscl_wb 261
75 smmu_gscl0 262
76 smmu_gscl1 263
77 smmu_gscl2 264
78 smmu_gscl3 265
79 mfc 266
80 smmu_mfcl 267
81 smmu_mfcr 268
82 rotator 269
83 jpeg 270
84 mdma1 271
85 smmu_rotator 272
86 smmu_jpeg 273
87 smmu_mdma1 274
88 pdma0 275
89 pdma1 276
90 sata 277
91 usbotg 278
92 mipi_hsi 279
93 sdmmc0 280
94 sdmmc1 281
95 sdmmc2 282
96 sdmmc3 283
97 sromc 284
98 usb2 285
99 usb3 286
100 sata_phyctrl 287
101 sata_phyi2c 288
102 uart0 289
103 uart1 290
104 uart2 291
105 uart3 292
106 uart4 293
107 i2c0 294
108 i2c1 295
109 i2c2 296
110 i2c3 297
111 i2c4 298
112 i2c5 299
113 i2c6 300
114 i2c7 301
115 i2c_hdmi 302
116 adc 303
117 spi0 304
118 spi1 305
119 spi2 306
120 i2s1 307
121 i2s2 308
122 pcm1 309
123 pcm2 310
124 pwm 311
125 spdif 312
126 ac97 313
127 hsi2c0 314
128 hsi2c1 315
129 hs12c2 316
130 hs12c3 317
131 chipid 318
132 sysreg 319
133 pmu 320
134 cmu_top 321
135 cmu_core 322
136 cmu_mem 323
137 tzpc0 324
138 tzpc1 325
139 tzpc2 326
140 tzpc3 327
141 tzpc4 328
142 tzpc5 329
143 tzpc6 330
144 tzpc7 331
145 tzpc8 332
146 tzpc9 333
147 hdmi_cec 334
148 mct 335
149 wdt 336
150 rtc 337
151 tmu 338
152 fimd1 339
153 mie1 340
154 dsim0 341
155 dp 342
156 mixer 343
157 hdmi 345
158
159Example 1: An example of a clock controller node is listed below.
160
161 clock: clock-controller@0x10010000 {
162 compatible = "samsung,exynos5250-clock";
163 reg = <0x10010000 0x30000>;
164 #clock-cells = <1>;
165 };
166
167Example 2: UART controller node that consumes the clock generated by the clock
168 controller. Refer to the standard clock bindings for information
169 about 'clocks' and 'clock-names' property.
170
171 serial@13820000 {
172 compatible = "samsung,exynos4210-uart";
173 reg = <0x13820000 0x100>;
174 interrupts = <0 54 0>;
175 clocks = <&clock 314>, <&clock 153>;
176 clock-names = "uart", "clk_uart_baud0";
177 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 000000000000..4499e9966bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
1* Samsung Exynos5440 Clock Controller
2
3The Exynos5440 clock controller generates and supplies clock to various
4controllers within the Exynos5440 SoC.
5
6Required Properties:
7
8- comptible: should be "samsung,exynos5440-clock".
9
10- reg: physical base address of the controller and length of memory mapped
11 region.
12
13- #clock-cells: should be 1.
14
15The following is the list of clocks generated by the controller. Each clock is
16assigned an identifier and client nodes use this identifier to specify the
17clock which they consume.
18
19
20 [Core Clocks]
21
22 Clock ID
23 ----------------------------
24
25 xtal 1
26 arm_clk 2
27
28 [Peripheral Clock Gates]
29
30 Clock ID
31 ----------------------------
32
33 spi_baud 16
34 pb0_250 17
35 pr0_250 18
36 pr1_250 19
37 b_250 20
38 b_125 21
39 b_200 22
40 sata 23
41 usb 24
42 gmac0 25
43 cs250 26
44 pb0_250_o 27
45 pr0_250_o 28
46 pr1_250_o 29
47 b_250_o 30
48 b_125_o 31
49 b_200_o 32
50 sata_o 33
51 usb_o 34
52 gmac0_o 35
53 cs250_o 36
54
55Example: An example of a clock controller node is listed below.
56
57 clock: clock-controller@0x10010000 {
58 compatible = "samsung,exynos5440-clock";
59 reg = <0x160000 0x10000>;
60 #clock-cells = <1>;
61 };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 67ec3d4ccc7f..bf0182d8da25 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,3 +21,24 @@ Required properties:
21 21
22 - samsung,mfc-l : Base address of the second memory bank used by MFC 22 - samsung,mfc-l : Base address of the second memory bank used by MFC
23 for DMA contiguous memory allocation and its size. 23 for DMA contiguous memory allocation and its size.
24
25Optional properties:
26 - samsung,power-domain : power-domain property defined with a phandle
27 to respective power domain.
28
29Example:
30SoC specific DT entry:
31
32mfc: codec@13400000 {
33 compatible = "samsung,mfc-v5";
34 reg = <0x13400000 0x10000>;
35 interrupts = <0 94 0>;
36 samsung,power-domain = <&pd_mfc>;
37};
38
39Board specific DT entry:
40
41codec@13400000 {
42 samsung,mfc-r = <0x43000000 0x800000>;
43 samsung,mfc-l = <0x51000000 0x800000>;
44};
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000000000000..f66fcddba46f
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,40 @@
1Samsung Exynos SoC USB controller
2
3The USB devices interface with USB controllers on Exynos SOCs.
4The device node has following properties.
5
6EHCI
7Required properties:
8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
9 EHCI controller in host mode.
10 - reg: physical base address of the controller and length of memory mapped
11 region.
12 - interrupts: interrupt number to the cpu.
13
14Optional properties:
15 - samsung,vbus-gpio: if present, specifies the GPIO that
16 needs to be pulled up for the bus to be powered.
17
18Example:
19
20 usb@12110000 {
21 compatible = "samsung,exynos4210-ehci";
22 reg = <0x12110000 0x100>;
23 interrupts = <0 71 0>;
24 samsung,vbus-gpio = <&gpx2 6 1 3 3>;
25 };
26
27OHCI
28Required properties:
29 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
30 OHCI companion controller in host mode.
31 - reg: physical base address of the controller and length of memory mapped
32 region.
33 - interrupts: interrupt number to the cpu.
34
35Example:
36 usb@12120000 {
37 compatible = "samsung,exynos4210-ohci";
38 reg = <0x12120000 0x100>;
39 interrupts = <0 71 0>;
40 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 17:02:44 -0500