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authorScott Wood <scottwood@freescale.com>2008-07-11 18:31:15 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-07-16 18:57:28 -0400
commit2dff41775decb9cb1f3a6ac577c78dc3eea60431 (patch)
treeb17ed988730723bd5434e6791ea034b15e813e2e /Documentation
parent8a0ca91e1db5de5eb5b18cfa919d52ff8be375af (diff)
powerpc: Document Freescale power management nodes, and the sleep property.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/powerpc/booting-without-of.txt142
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/pmc.txt63
2 files changed, 163 insertions, 42 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index de2e5c05d6e7..07ae2edff7c4 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -77,10 +77,12 @@ Table of Contents
77 3) OpenPIC Interrupt Controllers 77 3) OpenPIC Interrupt Controllers
78 4) ISA Interrupt Controllers 78 4) ISA Interrupt Controllers
79 79
80 VIII - Specifying GPIO information for devices 80 IX - Specifying GPIO information for devices
81 1) gpios property 81 1) gpios property
82 2) gpio-controller nodes 82 2) gpio-controller nodes
83 83
84 X - Specifying device power management information (sleep property)
85
84 Appendix A - Sample SOC node for MPC8540 86 Appendix A - Sample SOC node for MPC8540
85 87
86 88
@@ -2422,8 +2424,8 @@ encodings listed below:
2422 2 = high to low edge sensitive type enabled 2424 2 = high to low edge sensitive type enabled
2423 3 = low to high edge sensitive type enabled 2425 3 = low to high edge sensitive type enabled
2424 2426
2425VIII - Specifying GPIO information for devices 2427IX - Specifying GPIO information for devices
2426============================================== 2428============================================
2427 2429
24281) gpios property 24301) gpios property
2429----------------- 2431-----------------
@@ -2471,6 +2473,37 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
2471 gpio-controller; 2473 gpio-controller;
2472 }; 2474 };
2473 2475
2476X - Specifying Device Power Management Information (sleep property)
2477===================================================================
2478
2479Devices on SOCs often have mechanisms for placing devices into low-power
2480states that are decoupled from the devices' own register blocks. Sometimes,
2481this information is more complicated than a cell-index property can
2482reasonably describe. Thus, each device controlled in such a manner
2483may contain a "sleep" property which describes these connections.
2484
2485The sleep property consists of one or more sleep resources, each of
2486which consists of a phandle to a sleep controller, followed by a
2487controller-specific sleep specifier of zero or more cells.
2488
2489The semantics of what type of low power modes are possible are defined
2490by the sleep controller. Some examples of the types of low power modes
2491that may be supported are:
2492
2493 - Dynamic: The device may be disabled or enabled at any time.
2494 - System Suspend: The device may request to be disabled or remain
2495 awake during system suspend, but will not be disabled until then.
2496 - Permanent: The device is disabled permanently (until the next hard
2497 reset).
2498
2499Some devices may share a clock domain with each other, such that they should
2500only be suspended when none of the devices are in use. Where reasonable,
2501such nodes should be placed on a virtual bus, where the bus has the sleep
2502property. If the clock domain is shared among devices that cannot be
2503reasonably grouped in this manner, then create a virtual sleep controller
2504(similar to an interrupt nexus, except that defining a standardized
2505sleep-map should wait until its necessity is demonstrated).
2506
2474Appendix A - Sample SOC node for MPC8540 2507Appendix A - Sample SOC node for MPC8540
2475======================================== 2508========================================
2476 2509
@@ -2487,47 +2520,48 @@ not necessary as they are usually the same as the root node.
2487 reg = <e0000000 00003000>; 2520 reg = <e0000000 00003000>;
2488 bus-frequency = <0>; 2521 bus-frequency = <0>;
2489 2522
2490 mdio@24520 {
2491 reg = <24520 20>;
2492 device_type = "mdio";
2493 compatible = "gianfar";
2494
2495 ethernet-phy@0 {
2496 linux,phandle = <2452000>
2497 interrupt-parent = <40000>;
2498 interrupts = <35 1>;
2499 reg = <0>;
2500 device_type = "ethernet-phy";
2501 };
2502
2503 ethernet-phy@1 {
2504 linux,phandle = <2452001>
2505 interrupt-parent = <40000>;
2506 interrupts = <35 1>;
2507 reg = <1>;
2508 device_type = "ethernet-phy";
2509 };
2510
2511 ethernet-phy@3 {
2512 linux,phandle = <2452002>
2513 interrupt-parent = <40000>;
2514 interrupts = <35 1>;
2515 reg = <3>;
2516 device_type = "ethernet-phy";
2517 };
2518
2519 };
2520
2521 ethernet@24000 { 2523 ethernet@24000 {
2522 #size-cells = <0>; 2524 #address-cells = <1>;
2525 #size-cells = <1>;
2523 device_type = "network"; 2526 device_type = "network";
2524 model = "TSEC"; 2527 model = "TSEC";
2525 compatible = "gianfar"; 2528 compatible = "gianfar", "simple-bus";
2526 reg = <24000 1000>; 2529 reg = <24000 1000>;
2527 mac-address = [ 00 E0 0C 00 73 00 ]; 2530 mac-address = [ 00 E0 0C 00 73 00 ];
2528 interrupts = <d 3 e 3 12 3>; 2531 interrupts = <d 3 e 3 12 3>;
2529 interrupt-parent = <40000>; 2532 interrupt-parent = <40000>;
2530 phy-handle = <2452000>; 2533 phy-handle = <2452000>;
2534 sleep = <&pmc 00000080>;
2535 ranges;
2536
2537 mdio@24520 {
2538 reg = <24520 20>;
2539 compatible = "fsl,gianfar-mdio";
2540
2541 ethernet-phy@0 {
2542 linux,phandle = <2452000>
2543 interrupt-parent = <40000>;
2544 interrupts = <35 1>;
2545 reg = <0>;
2546 device_type = "ethernet-phy";
2547 };
2548
2549 ethernet-phy@1 {
2550 linux,phandle = <2452001>
2551 interrupt-parent = <40000>;
2552 interrupts = <35 1>;
2553 reg = <1>;
2554 device_type = "ethernet-phy";
2555 };
2556
2557 ethernet-phy@3 {
2558 linux,phandle = <2452002>
2559 interrupt-parent = <40000>;
2560 interrupts = <35 1>;
2561 reg = <3>;
2562 device_type = "ethernet-phy";
2563 };
2564 };
2531 }; 2565 };
2532 2566
2533 ethernet@25000 { 2567 ethernet@25000 {
@@ -2541,6 +2575,7 @@ not necessary as they are usually the same as the root node.
2541 interrupts = <13 3 14 3 18 3>; 2575 interrupts = <13 3 14 3 18 3>;
2542 interrupt-parent = <40000>; 2576 interrupt-parent = <40000>;
2543 phy-handle = <2452001>; 2577 phy-handle = <2452001>;
2578 sleep = <&pmc 00000040>;
2544 }; 2579 };
2545 2580
2546 ethernet@26000 { 2581 ethernet@26000 {
@@ -2554,15 +2589,33 @@ not necessary as they are usually the same as the root node.
2554 interrupts = <19 3>; 2589 interrupts = <19 3>;
2555 interrupt-parent = <40000>; 2590 interrupt-parent = <40000>;
2556 phy-handle = <2452002>; 2591 phy-handle = <2452002>;
2592 sleep = <&pmc 00000020>;
2557 }; 2593 };
2558 2594
2559 serial@4500 { 2595 serial@4500 {
2560 device_type = "serial"; 2596 #address-cells = <1>;
2561 compatible = "ns16550"; 2597 #size-cells = <1>;
2562 reg = <4500 100>; 2598 compatible = "fsl,mpc8540-duart", "simple-bus";
2563 clock-frequency = <0>; 2599 sleep = <&pmc 00000002>;
2564 interrupts = <1a 3>; 2600 ranges;
2565 interrupt-parent = <40000>; 2601
2602 serial@4500 {
2603 device_type = "serial";
2604 compatible = "ns16550";
2605 reg = <4500 100>;
2606 clock-frequency = <0>;
2607 interrupts = <1a 3>;
2608 interrupt-parent = <40000>;
2609 };
2610
2611 serial@4600 {
2612 device_type = "serial";
2613 compatible = "ns16550";
2614 reg = <4600 100>;
2615 clock-frequency = <0>;
2616 interrupts = <1a 3>;
2617 interrupt-parent = <40000>;
2618 };
2566 }; 2619 };
2567 2620
2568 pic@40000 { 2621 pic@40000 {
@@ -2581,6 +2634,11 @@ not necessary as they are usually the same as the root node.
2581 device_type = "i2c"; 2634 device_type = "i2c";
2582 compatible = "fsl-i2c"; 2635 compatible = "fsl-i2c";
2583 dfsrr; 2636 dfsrr;
2637 sleep = <&pmc 00000004>;
2584 }; 2638 };
2585 2639
2640 pmc: power@e0070 {
2641 compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
2642 reg = <e0070 20>;
2643 };
2586 }; 2644 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/pmc.txt b/Documentation/powerpc/dts-bindings/fsl/pmc.txt
new file mode 100644
index 000000000000..02f6f43ee1b7
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/pmc.txt
@@ -0,0 +1,63 @@
1* Power Management Controller
2
3Properties:
4- compatible: "fsl,<chip>-pmc".
5
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
9
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
13
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
17
18 Compatibility does not include bit assigments in SCCR/PMCDR/DEVDISR; these
19 bit assigments are indicated via the sleep specifier in each device's
20 sleep property.
21
22- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
23 is the PMC block, and the second resource is the Clock Configuration
24 block.
25
26 For devices compatible with "fsl,mpc8548-pmc", the first resource
27 is a 32-byte block beginning with DEVDISR.
28
29- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
30 resource is the PMC block interrupt.
31
32- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
33 this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
34 a wakeup source from deep sleep.
35
36Sleep specifiers:
37
38 fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
39 that is set in the cell, the corresponding bit in SCCR will be saved
40 and cleared on suspend, and restored on resume. This sleep controller
41 supports disabling and resuming devices at any time.
42
43 fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
44 which will be ORed into PMCDR upon suspend, and cleared from PMCDR
45 upon resume. The first two cells are as described for fsl,mpc8578-pmc.
46 This sleep controller only supports disabling devices during system
47 sleep, or permanently.
48
49 fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
50 first of which will be ORed into DEVDISR (and the second into
51 DEVDISR2, if present -- this cell should be zero or absent if the
52 hardware does not have DEVDISR2) upon a request for permanent device
53 disabling. This sleep controller does not support configuring devices
54 to disable during system sleep (unless supported by another compatible
55 match), or dynamically.
56
57Example:
58
59 power@b00 {
60 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
61 reg = <0xb00 0x100 0xa00 0x100>;
62 interrupts = <80 8>;
63 };