diff options
author | HighPoint Linux Team <linux@highpoint-tech.com> | 2009-09-11 05:21:27 -0400 |
---|---|---|
committer | James Bottomley <James.Bottomley@suse.de> | 2009-10-02 10:45:22 -0400 |
commit | 3bfc13c239fd56ebc1ac98a914c6c6b8b0045478 (patch) | |
tree | 58568a4279e233de914a52fd53c3c5414f83a3d1 /Documentation | |
parent | c0630f76d09131d606857a3da39739791d2c7b35 (diff) |
[SCSI] hptiop: Add RR44xx adapter support
Most code changes were made to support RR44xx adapters.
- add more PCI device ID.
- using PCI BAR[2] to access RR44xx IOP.
- using PCI BAR[0] to check and clear RR44xx IRQ.
Signed-off-by: HighPoint Linux Team <linux@highpoint-tech.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/scsi/hptiop.txt | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/Documentation/scsi/hptiop.txt b/Documentation/scsi/hptiop.txt index a6eb4add1be6..9605179711f4 100644 --- a/Documentation/scsi/hptiop.txt +++ b/Documentation/scsi/hptiop.txt | |||
@@ -3,6 +3,25 @@ HIGHPOINT ROCKETRAID 3xxx/4xxx ADAPTER DRIVER (hptiop) | |||
3 | Controller Register Map | 3 | Controller Register Map |
4 | ------------------------- | 4 | ------------------------- |
5 | 5 | ||
6 | For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2: | ||
7 | |||
8 | BAR0 offset Register | ||
9 | 0x11C5C Link Interface IRQ Set | ||
10 | 0x11C60 Link Interface IRQ Clear | ||
11 | |||
12 | BAR2 offset Register | ||
13 | 0x10 Inbound Message Register 0 | ||
14 | 0x14 Inbound Message Register 1 | ||
15 | 0x18 Outbound Message Register 0 | ||
16 | 0x1C Outbound Message Register 1 | ||
17 | 0x20 Inbound Doorbell Register | ||
18 | 0x24 Inbound Interrupt Status Register | ||
19 | 0x28 Inbound Interrupt Mask Register | ||
20 | 0x30 Outbound Interrupt Status Register | ||
21 | 0x34 Outbound Interrupt Mask Register | ||
22 | 0x40 Inbound Queue Port | ||
23 | 0x44 Outbound Queue Port | ||
24 | |||
6 | For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: | 25 | For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: |
7 | 26 | ||
8 | BAR0 offset Register | 27 | BAR0 offset Register |
@@ -93,7 +112,7 @@ The driver exposes following sysfs attributes: | |||
93 | 112 | ||
94 | 113 | ||
95 | ----------------------------------------------------------------------------- | 114 | ----------------------------------------------------------------------------- |
96 | Copyright (C) 2006-2007 HighPoint Technologies, Inc. All Rights Reserved. | 115 | Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved. |
97 | 116 | ||
98 | This file is distributed in the hope that it will be useful, | 117 | This file is distributed in the hope that it will be useful, |
99 | but WITHOUT ANY WARRANTY; without even the implied warranty of | 118 | but WITHOUT ANY WARRANTY; without even the implied warranty of |