diff options
| author | Thierry Reding <thierry.reding@avionic-design.de> | 2012-10-01 02:41:23 -0400 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@avionic-design.de> | 2012-10-07 06:11:53 -0400 |
| commit | 85f8879ca4f3d26a7f473522101fb74a79bda3f2 (patch) | |
| tree | 26bc8e984bb47a8a154fabd58c6642fe9facd882 /Documentation | |
| parent | c2d476a98f71c55e9acdca1d5a1080a22c0622af (diff) | |
pwm: dt: Fix description of second PWM cell
The second cell in the PWM specifier denotes the period in nanoseconds,
not the duty cycle. The latter can be freely configured at runtime and
a PWM with a fixed duty cycle would be rather pointless.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index 9b9b18514b61..8522bfbccfd7 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt | |||
| @@ -4,7 +4,7 @@ Required properties: | |||
| 4 | - compatible: should be "fsl,<soc>-pwm" | 4 | - compatible: should be "fsl,<soc>-pwm" |
| 5 | - reg: physical base address and length of the controller's registers | 5 | - reg: physical base address and length of the controller's registers |
| 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index |
| 7 | of the PWM to use and the second cell is the duty cycle in nanoseconds. | 7 | of the PWM to use and the second cell is the period in nanoseconds. |
| 8 | - interrupts: The interrupt for the pwm controller | 8 | - interrupts: The interrupt for the pwm controller |
| 9 | 9 | ||
| 10 | Example: | 10 | Example: |
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt index b16f4a57d111..d7946be6cd27 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt | |||
| @@ -4,7 +4,7 @@ Required properties: | |||
| 4 | - compatible: should be "fsl,imx23-pwm" | 4 | - compatible: should be "fsl,imx23-pwm" |
| 5 | - reg: physical base address and length of the controller's registers | 5 | - reg: physical base address and length of the controller's registers |
| 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index |
| 7 | of the PWM to use and the second cell is the duty cycle in nanoseconds. | 7 | of the PWM to use and the second cell is the period in nanoseconds. |
| 8 | - fsl,pwm-number: the number of PWM devices | 8 | - fsl,pwm-number: the number of PWM devices |
| 9 | 9 | ||
| 10 | Example: | 10 | Example: |
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index bbbeedb4ec05..01438ecd6628 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | |||
| @@ -7,7 +7,7 @@ Required properties: | |||
| 7 | - reg: physical base address and length of the controller's registers | 7 | - reg: physical base address and length of the controller's registers |
| 8 | - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The | 8 | - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The |
| 9 | first cell specifies the per-chip index of the PWM to use and the second | 9 | first cell specifies the per-chip index of the PWM to use and the second |
| 10 | cell is the duty cycle in nanoseconds. | 10 | cell is the period in nanoseconds. |
| 11 | 11 | ||
| 12 | Example: | 12 | Example: |
| 13 | 13 | ||