aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 14:02:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 14:02:18 -0400
commitfcba914542082b272f31c8e4c40000b88ed3208d (patch)
treefb28069bf571d93420daafd501b4e97f221d526c /Documentation
parenta8c4b90e670be3b01e9395c7310639c8109fc77e (diff)
parent5c5f0421a8eea5bdaba9b9313c5bb4833aeb39cd (diff)
Merge tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates (part 3) from Arnd Bergmann: "This is the third and smallest of the SoC specific updates. Changes include: - SMP support for the Xilinx zynq platform - Smaller imx changes - LPAE support for mvebu - Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more." * tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: imx: reset_controller may be disabled ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt14
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/reset/fsl,imx-src.txt49
-rw-r--r--Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt3
4 files changed, 68 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 2a0c904c46ae..d71b4b2c077d 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -38,7 +38,6 @@ clocks and IDs.
38 usb_phy_podf 23 38 usb_phy_podf 23
39 cpu_podf 24 39 cpu_podf 24
40 di_pred 25 40 di_pred 25
41 tve_di 26
42 tve_s 27 41 tve_s 27
43 uart1_ipg_gate 28 42 uart1_ipg_gate 28
44 uart1_per_gate 29 43 uart1_per_gate 29
@@ -172,6 +171,19 @@ clocks and IDs.
172 can1_serial_gate 157 171 can1_serial_gate 157
173 can1_ipg_gate 158 172 can1_ipg_gate 158
174 owire_gate 159 173 owire_gate 159
174 gpu3d_s 160
175 gpu2d_s 161
176 gpu3d_gate 162
177 gpu2d_gate 163
178 garb_gate 164
179 cko1_sel 165
180 cko1_podf 166
181 cko1 167
182 cko2_sel 168
183 cko2_podf 169
184 cko2 170
185 srtc_gate 171
186 pata_gate 172
175 187
176Examples (for mx53): 188Examples (for mx53):
177 189
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 969b38e06ad3..6deb6fd1c7cd 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -205,6 +205,9 @@ clocks and IDs.
205 enet_ref 190 205 enet_ref 190
206 usbphy1_gate 191 206 usbphy1_gate 191
207 usbphy2_gate 192 207 usbphy2_gate 192
208 pll4_post_div 193
209 pll5_post_div 194
210 pll5_video_div 195
208 211
209Examples: 212Examples:
210 213
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
new file mode 100644
index 000000000000..13301777e11c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
@@ -0,0 +1,49 @@
1Freescale i.MX System Reset Controller
2======================================
3
4Please also refer to reset.txt in this directory for common reset
5controller binding usage.
6
7Required properties:
8- compatible: Should be "fsl,<chip>-src"
9- reg: should be register base and length as documented in the
10 datasheet
11- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
12 in this order.
13- #reset-cells: 1, see below
14
15example:
16
17src: src@020d8000 {
18 compatible = "fsl,imx6q-src";
19 reg = <0x020d8000 0x4000>;
20 interrupts = <0 91 0x04 0 96 0x04>;
21 #reset-cells = <1>;
22};
23
24Specifying reset lines connected to IP modules
25==============================================
26
27The system reset controller can be used to reset the GPU, VPU,
28IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
29nodes should specify the reset line on the SRC in their resets
30property, containing a phandle to the SRC device node and a
31RESET_INDEX specifying which module to reset, as described in
32reset.txt
33
34example:
35
36 ipu1: ipu@02400000 {
37 resets = <&src 2>;
38 };
39 ipu2: ipu@02800000 {
40 resets = <&src 4>;
41 };
42
43The following RESET_INDEX values are valid for i.MX5:
44GPU_RESET 0
45VPU_RESET 1
46IPU1_RESET 2
47OPEN_VG_RESET 3
48The following additional RESET_INDEX value is valid for i.MX6:
49IPU2_RESET 4
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index 8071ac20d4b3..b876d4925a57 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -8,6 +8,8 @@ Required properties:
8- interrupts: Should contain sync interrupt and error interrupt, 8- interrupts: Should contain sync interrupt and error interrupt,
9 in this order. 9 in this order.
10- #crtc-cells: 1, See below 10- #crtc-cells: 1, See below
11- resets: phandle pointing to the system reset controller and
12 reset line index, see reset/fsl,imx-src.txt for details
11 13
12example: 14example:
13 15
@@ -16,6 +18,7 @@ ipu: ipu@18000000 {
16 compatible = "fsl,imx53-ipu"; 18 compatible = "fsl,imx53-ipu";
17 reg = <0x18000000 0x080000000>; 19 reg = <0x18000000 0x080000000>;
18 interrupts = <11 10>; 20 interrupts = <11 10>;
21 resets = <&src 2>;
19}; 22};
20 23
21Parallel display support 24Parallel display support