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author | Marek Szyprowski <m.szyprowski@samsung.com> | 2011-12-23 03:30:47 -0500 |
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committer | Marek Szyprowski <m.szyprowski@samsung.com> | 2012-03-28 10:36:43 -0400 |
commit | 8a4134322bd429d24f71147eb59a47a981e8f63a (patch) | |
tree | bce9920c5f163669666693cd9d307bd865ad2bb1 /Documentation | |
parent | 9adc537452e1e341cabd39a02d4788d3c510b0e2 (diff) |
common: DMA-mapping: add WRITE_COMBINE attribute
DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
buffered to improve performance. It will be used by the replacement for
ARM/ARV32 specific dma_alloc_writecombine() function.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/DMA-attributes.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index b768cc0e402b..811a5d458dae 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt | |||
@@ -31,3 +31,13 @@ may be weakly ordered, that is that reads and writes may pass each other. | |||
31 | Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, | 31 | Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, |
32 | those that do not will simply ignore the attribute and exhibit default | 32 | those that do not will simply ignore the attribute and exhibit default |
33 | behavior. | 33 | behavior. |
34 | |||
35 | DMA_ATTR_WRITE_COMBINE | ||
36 | ---------------------- | ||
37 | |||
38 | DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be | ||
39 | buffered to improve performance. | ||
40 | |||
41 | Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, | ||
42 | those that do not will simply ignore the attribute and exhibit default | ||
43 | behavior. | ||