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authorvenkatesh.pallipadi@intel.com <venkatesh.pallipadi@intel.com>2008-03-18 20:00:13 -0400
committerIngo Molnar <mingo@elte.hu>2008-04-17 11:41:19 -0400
commitd27554d874c7eeb14c8bfecdc39c3a8618cd8d32 (patch)
tree363b54b053e13677fc199c01a9e76ed41edf4500 /Documentation/x86
parent7de6a4cdac6341807261a33896f9ab5a502a4e74 (diff)
x86: PAT documentation
Documentation about PAT related interfaces, intended usage and memory attribute relationship. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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1
2PAT (Page Attribute Table)
3
4x86 Page Attribute Table (PAT) allows for setting the memory attribute at the
5page level granularity. PAT is complementary to the MTRR settings which allows
6for setting of memory types over physical address ranges. However, PAT is
7more flexible than MTRR due to its capability to set attributes at page level
8and also due to the fact that there are no hardware limitations on number of
9such attribute settings allowed. Added flexibility comes with guidelines for
10not having memory type aliasing for the same physical memory with multiple
11virtual addresses.
12
13PAT allows for different types of memory attributes. The most commonly used
14ones that will be supported at this time are Write-back, Uncached,
15Write-combined and Uncached Minus.
16
17There are many different APIs in the kernel that allows setting of memory
18attributes at the page level. In order to avoid aliasing, these interfaces
19should be used thoughtfully. Below is a table of interfaces available,
20their intended usage and their memory attribute relationships. Internally,
21these APIs use a reserve_memtype()/free_memtype() interface on the physical
22address range to avoid any aliasing.
23
24
25-------------------------------------------------------------------
26API | RAM | ACPI,... | Reserved/Holes |
27-----------------------|----------|------------|------------------|
28 | | | |
29ioremap | -- | UC | UC |
30 | | | |
31ioremap_cache | -- | WB | WB |
32 | | | |
33ioremap_nocache | -- | UC | UC |
34 | | | |
35ioremap_wc | -- | -- | WC |
36 | | | |
37set_memory_uc | UC | -- | -- |
38 set_memory_wb | | | |
39 | | | |
40set_memory_wc | WC | -- | -- |
41 set_memory_wb | | | |
42 | | | |
43pci sysfs resource | -- | -- | UC |
44 | | | |
45pci sysfs resource_wc | -- | -- | WC |
46 is IORESOURCE_PREFETCH| | | |
47 | | | |
48pci proc | -- | -- | UC |
49 !PCIIOC_WRITE_COMBINE | | | |
50 | | | |
51pci proc | -- | -- | WC |
52 PCIIOC_WRITE_COMBINE | | | |
53 | | | |
54/dev/mem | -- | UC | UC |
55 read-write | | | |
56 | | | |
57/dev/mem | -- | UC | UC |
58 mmap SYNC flag | | | |
59 | | | |
60/dev/mem | -- | WB/WC/UC | WB/WC/UC |
61 mmap !SYNC flag | |(from exist-| (from exist- |
62 and | | ing alias)| ing alias) |
63 any alias to this area| | | |
64 | | | |
65/dev/mem | -- | WB | WB |
66 mmap !SYNC flag | | | |
67 no alias to this area | | | |
68 and | | | |
69 MTRR says WB | | | |
70 | | | |
71/dev/mem | -- | -- | UC_MINUS |
72 mmap !SYNC flag | | | |
73 no alias to this area | | | |
74 and | | | |
75 MTRR says !WB | | | |
76 | | | |
77-------------------------------------------------------------------
78
79Notes:
80
81-- in the above table mean "Not suggested usage for the API". Some of the --'s
82are strictly enforced by the kernel. Some others are not really enforced
83today, but may be enforced in future.
84
85For ioremap and pci access through /sys or /proc - The actual type returned
86can be more restrictive, in case of any existing aliasing for that address.
87For example: If there is an existing uncached mapping, a new ioremap_wc can
88return uncached mapping in place of write-combine requested.
89
90set_memory_[uc|wc] and set_memory_wb should be used in pairs, where driver will
91first make a region uc or wc and switch it back to wb after use.
92
93Over time writes to /proc/mtrr will be deprecated in favor of using PAT based
94interfaces. Users writing to /proc/mtrr are suggested to use above interfaces.
95
96Drivers should use ioremap_[uc|wc] to access PCI BARs with [uc|wc] access
97types.
98
99Drivers should use set_memory_[uc|wc] to set access type for RAM ranges.
100