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authorPaolo Ornati <ornati@fastwebnet.it>2006-10-03 16:57:56 -0400
committerAdrian Bunk <bunk@stusta.de>2006-10-03 16:57:56 -0400
commit670e9f34ee3c7e052514c85014d2fdd99b672cdc (patch)
tree41f82a763ba6d5ca2fcb84d6a05808d095d4d051 /Documentation/spi/pxa2xx
parent53cb47268e6b38180d9f253527135e1c69c5d310 (diff)
Documentation: remove duplicated words
Remove many duplicated words under Documentation/ and do other small cleanups. Examples: "and and" --> "and" "in in" --> "in" "the the" --> "the" "the the" --> "to the" ... Signed-off-by: Paolo Ornati <ornati@fastwebnet.it> Signed-off-by: Adrian Bunk <bunk@stusta.de>
Diffstat (limited to 'Documentation/spi/pxa2xx')
-rw-r--r--Documentation/spi/pxa2xx6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx
index 9c45f3df2e18..a1e0ee20f595 100644
--- a/Documentation/spi/pxa2xx
+++ b/Documentation/spi/pxa2xx
@@ -124,12 +124,12 @@ use a value of 8.
124The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle 124The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle
125trailing bytes in the SSP receiver fifo. The correct value for this field is 125trailing bytes in the SSP receiver fifo. The correct value for this field is
126dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific 126dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
127slave device. Please note the the PXA2xx SSP 1 does not support trailing byte 127slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
128timeouts and must busy-wait any trailing bytes. 128timeouts and must busy-wait any trailing bytes.
129 129
130The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting 130The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
131into internal loopback mode. In this mode the SSP controller internally 131into internal loopback mode. In this mode the SSP controller internally
132connects the SSPTX pin the the SSPRX pin. This is useful for initial setup 132connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
133testing. 133testing.
134 134
135The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific 135The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
@@ -208,7 +208,7 @@ DMA and PIO I/O Support
208----------------------- 208-----------------------
209The pxa2xx_spi driver support both DMA and interrupt driven PIO message 209The pxa2xx_spi driver support both DMA and interrupt driven PIO message
210transfers. The driver defaults to PIO mode and DMA transfers must enabled by 210transfers. The driver defaults to PIO mode and DMA transfers must enabled by
211setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and and 211setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and
212ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero. The DMA 212ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero. The DMA
213mode support both coherent and stream based DMA mappings. 213mode support both coherent and stream based DMA mappings.
214 214