aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/powerpc
diff options
context:
space:
mode:
authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-09-15 17:44:00 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-11-11 22:43:30 -0500
commit8c68e2f7885b22f0a63bf087752a46b690d6b6ea (patch)
tree5dcb238c4bb85f43ab46d9c33ad3c060824773cf /Documentation/powerpc
parent3cfee0aaa1c7767e1b85272a0621e3a78ece7879 (diff)
powerpc/86xx: Add power management support for MPC8610HPCD boards
This patch adds needed nodes and properties to support suspend/resume on the MPC8610HPCD boards. There is a dedicated switch (SW9) that is used to wake up the boards. By default the SW9 button is routed to IRQ8, but could be re-routed (via PIXIS) to sreset. With 'no_console_suspend' kernel command line argument specified, the board is also able to wakeup upon serial port input. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Scott Wood <scottwood@freescale.com> [dts] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/board.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index e8b5bc24d0ac..39e941515a36 100644
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -20,12 +20,16 @@ Required properities:
20- compatible : should be "fsl,fpga-pixis". 20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the length of the FPPGA register 21- reg : should contain the address and the length of the FPPGA register
22 set. 22 set.
23- interrupt-parent: should specify phandle for the interrupt controller.
24- interrupts : should specify event (wakeup) IRQ.
23 25
24Example (MPC8610HPCD): 26Example (MPC8610HPCD):
25 27
26 board-control@e8000000 { 28 board-control@e8000000 {
27 compatible = "fsl,fpga-pixis"; 29 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>; 30 reg = <0xe8000000 32>;
31 interrupt-parent = <&mpic>;
32 interrupts = <8 8>;
29 }; 33 };
30 34
31* Freescale BCSR GPIO banks 35* Freescale BCSR GPIO banks