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authorAnatolij Gustschin <agust@denx.de>2010-07-23 00:00:38 -0400
committerGrant Likely <grant.likely@secretlab.ca>2010-08-01 19:06:44 -0400
commita027b33348df3512d7680eed29bada1247f01ad7 (patch)
tree665b11497f38e6a308afc3e955b377980690e960 /Documentation/powerpc
parent4b5006ec7bb73cd9d4c8a723d484b4c87fad4123 (diff)
powerpc/5121: doc/dts-bindings: update doc of FSL DIU bindings
Update compatible and interrupt properties description. Furthermore an example for the MPC5121 has been added. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'Documentation/powerpc')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/diu.txt14
1 files changed, 12 insertions, 2 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/diu.txt b/Documentation/powerpc/dts-bindings/fsl/diu.txt
index deb35de70988..326cddfd7c25 100644
--- a/Documentation/powerpc/dts-bindings/fsl/diu.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/diu.txt
@@ -4,10 +4,12 @@ The Freescale DIU is a LCD controller, with proper hardware, it can also
4drive DVI monitors. 4drive DVI monitors.
5 5
6Required properties: 6Required properties:
7- compatible : should be "fsl-diu". 7- compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
8- reg : should contain at least address and length of the DIU register 8- reg : should contain at least address and length of the DIU register
9 set. 9 set.
10- Interrupts : one DIU interrupt should be describe here. 10- interrupts : one DIU interrupt should be described here.
11- interrupt-parent : the phandle for the interrupt controller that
12 services interrupts for this device.
11 13
12Example (MPC8610HPCD): 14Example (MPC8610HPCD):
13 display@2c000 { 15 display@2c000 {
@@ -16,3 +18,11 @@ Example (MPC8610HPCD):
16 interrupts = <72 2>; 18 interrupts = <72 2>;
17 interrupt-parent = <&mpic>; 19 interrupt-parent = <&mpic>;
18 }; 20 };
21
22Example for MPC5121:
23 display@2100 {
24 compatible = "fsl,mpc5121-diu";
25 reg = <0x2100 0x100>;
26 interrupts = <64 0x8>;
27 interrupt-parent = <&ipic>;
28 };