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authorJochen Friedrich <jochen@scram.de>2008-07-05 07:29:28 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-07-16 18:57:40 -0400
commitade254d7f05cb74ab0a951ab105bc9ae872f045e (patch)
tree7543d4f28d59c57c633a5d521d1c13708f591cb7 /Documentation/powerpc/dts-bindings
parent89ae5b2b9357cd715ab25df50e5fa56ae30aaf80 (diff)
powerpc: Add documentation for CPM GPIO banks
Signed-off-by: Jochen Friedrich <jochen@scram.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc/dts-bindings')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt38
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt
new file mode 100644
index 000000000000..1815dfede1bc
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt
@@ -0,0 +1,38 @@
1Every GPIO controller node must have #gpio-cells property defined,
2this information will be used to translate gpio-specifiers.
3
4On CPM1 devices, all ports are using slightly different register layouts.
5Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
6
7On CPM2 devices, all ports are 32bit ports and use a common register layout.
8
9Required properties:
10- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13- #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional paramters (currently unused).
15- gpio-controller : Marks the port as GPIO controller.
16
17Example of three SOC GPIO banks defined as gpio-controller nodes:
18
19 CPM1_PIO_A: gpio-controller@950 {
20 #gpio-cells = <2>;
21 compatible = "fsl,cpm1-pario-bank-a";
22 reg = <0x950 0x10>;
23 gpio-controller;
24 };
25
26 CPM1_PIO_B: gpio-controller@ab8 {
27 #gpio-cells = <2>;
28 compatible = "fsl,cpm1-pario-bank-b";
29 reg = <0xab8 0x10>;
30 gpio-controller;
31 };
32
33 CPM1_PIO_E: gpio-controller@ac8 {
34 #gpio-cells = <2>;
35 compatible = "fsl,cpm1-pario-bank-e";
36 reg = <0xac8 0x18>;
37 gpio-controller;
38 };