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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-02-05 14:04:47 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-02-06 11:48:44 -0500
commit34bcda616e5308a0633d5bfabcc090d7aa09b494 (patch)
tree5625986b8f6806da4912af34fb2d3425e4d3705b /Documentation/powerpc/dts-bindings/fsl
parent960d82aa5ba971aa9da86a41881cb8dc8f96e397 (diff)
powerpc: Document FSL eSDHC bindings
This patch documents OF bindings for the Freescale Enhanced Secure Digital Host Controller. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc/dts-bindings/fsl')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/esdhc.txt24
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diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
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1* Freescale Enhanced Secure Digital Host Controller (eSDHC)
2
3The Enhanced Secure Digital Host Controller provides an interface
4for MMC, SD, and SDIO types of memory cards.
5
6Required properties:
7 - compatible : should be
8 "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
9 "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
10 - reg : should contain eSDHC registers location and length.
11 - interrupts : should contain eSDHC interrupt.
12 - interrupt-parent : interrupt source phandle.
13 - clock-frequency : specifies eSDHC base clock frequency.
14
15Example:
16
17sdhci@2e000 {
18 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
19 reg = <0x2e000 0x1000>;
20 interrupts = <42 0x8>;
21 interrupt-parent = <&ipic>;
22 /* Filled in by U-Boot */
23 clock-frequency = <0>;
24};