diff options
author | Paul Mackerras <paulus@samba.org> | 2007-11-07 22:28:14 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2007-11-07 22:28:14 -0500 |
commit | 688016f4e2028e3c2c27e959ad001536e10ee2c5 (patch) | |
tree | f45baa7b2c115f1297b4ad8d30b306204ef5e537 /Documentation/powerpc/booting-without-of.txt | |
parent | 2c84b4076c0cbbc44ffea2ae1da2a801fb23f081 (diff) | |
parent | 29273158f82020241d9a6539d6cef9cf926654c9 (diff) |
Merge branch 'for-2.6.24' of master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge
Diffstat (limited to 'Documentation/powerpc/booting-without-of.txt')
-rw-r--r-- | Documentation/powerpc/booting-without-of.txt | 261 |
1 files changed, 261 insertions, 0 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index 2233e3d5e5f3..ac1be25c1e25 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt | |||
@@ -52,6 +52,7 @@ Table of Contents | |||
52 | i) Freescale QUICC Engine module (QE) | 52 | i) Freescale QUICC Engine module (QE) |
53 | j) CFI or JEDEC memory-mapped NOR flash | 53 | j) CFI or JEDEC memory-mapped NOR flash |
54 | k) Global Utilities Block | 54 | k) Global Utilities Block |
55 | l) Xilinx IP cores | ||
55 | 56 | ||
56 | VII - Specifying interrupt information for devices | 57 | VII - Specifying interrupt information for devices |
57 | 1) interrupts property | 58 | 1) interrupts property |
@@ -2252,6 +2253,266 @@ platforms are moved over to use the flattened-device-tree model. | |||
2252 | available. | 2253 | available. |
2253 | For Axon: 0x0000012a | 2254 | For Axon: 0x0000012a |
2254 | 2255 | ||
2256 | l) Xilinx IP cores | ||
2257 | |||
2258 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | ||
2259 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | ||
2260 | of standard device types (network, serial, etc.) and miscellanious | ||
2261 | devices (gpio, LCD, spi, etc). Also, since these devices are | ||
2262 | implemented within the fpga fabric every instance of the device can be | ||
2263 | synthesised with different options that change the behaviour. | ||
2264 | |||
2265 | Each IP-core has a set of parameters which the FPGA designer can use to | ||
2266 | control how the core is synthesized. Historically, the EDK tool would | ||
2267 | extract the device parameters relevant to device drivers and copy them | ||
2268 | into an 'xparameters.h' in the form of #define symbols. This tells the | ||
2269 | device drivers how the IP cores are configured, but it requres the kernel | ||
2270 | to be recompiled every time the FPGA bitstream is resynthesized. | ||
2271 | |||
2272 | The new approach is to export the parameters into the device tree and | ||
2273 | generate a new device tree each time the FPGA bitstream changes. The | ||
2274 | parameters which used to be exported as #defines will now become | ||
2275 | properties of the device node. In general, device nodes for IP-cores | ||
2276 | will take the following form: | ||
2277 | |||
2278 | (name)@(base-address) { | ||
2279 | compatible = "xlnx,(ip-core-name)-(HW_VER)" | ||
2280 | [, (list of compatible devices), ...]; | ||
2281 | reg = <(baseaddr) (size)>; | ||
2282 | interrupt-parent = <&interrupt-controller-phandle>; | ||
2283 | interrupts = < ... >; | ||
2284 | xlnx,(parameter1) = "(string-value)"; | ||
2285 | xlnx,(parameter2) = <(int-value)>; | ||
2286 | }; | ||
2287 | |||
2288 | (ip-core-name): the name of the ip block (given after the BEGIN | ||
2289 | directive in system.mhs). Should be in lowercase | ||
2290 | and all underscores '_' converted to dashes '-'. | ||
2291 | (name): is derived from the "PARAMETER INSTANCE" value. | ||
2292 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | ||
2293 | dropped from the parameter name, the name is converted | ||
2294 | to lowercase and all underscore '_' characters are | ||
2295 | converted to dashes '-'. | ||
2296 | (baseaddr): the C_BASEADDR parameter. | ||
2297 | (HW_VER): from the HW_VER parameter. | ||
2298 | (size): equals C_HIGHADDR - C_BASEADDR + 1 | ||
2299 | |||
2300 | Typically, the compatible list will include the exact IP core version | ||
2301 | followed by an older IP core version which implements the same | ||
2302 | interface or any other device with the same interface. | ||
2303 | |||
2304 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | ||
2305 | |||
2306 | For example, the following block from system.mhs: | ||
2307 | |||
2308 | BEGIN opb_uartlite | ||
2309 | PARAMETER INSTANCE = opb_uartlite_0 | ||
2310 | PARAMETER HW_VER = 1.00.b | ||
2311 | PARAMETER C_BAUDRATE = 115200 | ||
2312 | PARAMETER C_DATA_BITS = 8 | ||
2313 | PARAMETER C_ODD_PARITY = 0 | ||
2314 | PARAMETER C_USE_PARITY = 0 | ||
2315 | PARAMETER C_CLK_FREQ = 50000000 | ||
2316 | PARAMETER C_BASEADDR = 0xEC100000 | ||
2317 | PARAMETER C_HIGHADDR = 0xEC10FFFF | ||
2318 | BUS_INTERFACE SOPB = opb_7 | ||
2319 | PORT OPB_Clk = CLK_50MHz | ||
2320 | PORT Interrupt = opb_uartlite_0_Interrupt | ||
2321 | PORT RX = opb_uartlite_0_RX | ||
2322 | PORT TX = opb_uartlite_0_TX | ||
2323 | PORT OPB_Rst = sys_bus_reset_0 | ||
2324 | END | ||
2325 | |||
2326 | becomes the following device tree node: | ||
2327 | |||
2328 | opb-uartlite-0@ec100000 { | ||
2329 | device_type = "serial"; | ||
2330 | compatible = "xlnx,opb-uartlite-1.00.b"; | ||
2331 | reg = <ec100000 10000>; | ||
2332 | interrupt-parent = <&opb-intc>; | ||
2333 | interrupts = <1 0>; // got this from the opb_intc parameters | ||
2334 | current-speed = <d#115200>; // standard serial device prop | ||
2335 | clock-frequency = <d#50000000>; // standard serial device prop | ||
2336 | xlnx,data-bits = <8>; | ||
2337 | xlnx,odd-parity = <0>; | ||
2338 | xlnx,use-parity = <0>; | ||
2339 | }; | ||
2340 | |||
2341 | Some IP cores actually implement 2 or more logical devices. In this case, | ||
2342 | the device should still describe the whole IP core with a single node | ||
2343 | and add a child node for each logical device. The ranges property can | ||
2344 | be used to translate from parent IP-core to the registers of each device. | ||
2345 | (Note: this makes the assumption that both logical devices have the same | ||
2346 | bus binding. If this is not true, then separate nodes should be used for | ||
2347 | each logical device). The 'cell-index' property can be used to enumerate | ||
2348 | logical devices within an IP core. For example, the following is the | ||
2349 | system.mhs entry for the dual ps2 controller found on the ml403 reference | ||
2350 | design. | ||
2351 | |||
2352 | BEGIN opb_ps2_dual_ref | ||
2353 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | ||
2354 | PARAMETER HW_VER = 1.00.a | ||
2355 | PARAMETER C_BASEADDR = 0xA9000000 | ||
2356 | PARAMETER C_HIGHADDR = 0xA9001FFF | ||
2357 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2358 | PORT Sys_Intr1 = ps2_1_intr | ||
2359 | PORT Sys_Intr2 = ps2_2_intr | ||
2360 | PORT Clkin1 = ps2_clk_rx_1 | ||
2361 | PORT Clkin2 = ps2_clk_rx_2 | ||
2362 | PORT Clkpd1 = ps2_clk_tx_1 | ||
2363 | PORT Clkpd2 = ps2_clk_tx_2 | ||
2364 | PORT Rx1 = ps2_d_rx_1 | ||
2365 | PORT Rx2 = ps2_d_rx_2 | ||
2366 | PORT Txpd1 = ps2_d_tx_1 | ||
2367 | PORT Txpd2 = ps2_d_tx_2 | ||
2368 | END | ||
2369 | |||
2370 | It would result in the following device tree nodes: | ||
2371 | |||
2372 | opb_ps2_dual_ref_0@a9000000 { | ||
2373 | ranges = <0 a9000000 2000>; | ||
2374 | // If this device had extra parameters, then they would | ||
2375 | // go here. | ||
2376 | ps2@0 { | ||
2377 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
2378 | reg = <0 40>; | ||
2379 | interrupt-parent = <&opb-intc>; | ||
2380 | interrupts = <3 0>; | ||
2381 | cell-index = <0>; | ||
2382 | }; | ||
2383 | ps2@1000 { | ||
2384 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
2385 | reg = <1000 40>; | ||
2386 | interrupt-parent = <&opb-intc>; | ||
2387 | interrupts = <3 0>; | ||
2388 | cell-index = <0>; | ||
2389 | }; | ||
2390 | }; | ||
2391 | |||
2392 | Also, the system.mhs file defines bus attachments from the processor | ||
2393 | to the devices. The device tree structure should reflect the bus | ||
2394 | attachments. Again an example; this system.mhs fragment: | ||
2395 | |||
2396 | BEGIN ppc405_virtex4 | ||
2397 | PARAMETER INSTANCE = ppc405_0 | ||
2398 | PARAMETER HW_VER = 1.01.a | ||
2399 | BUS_INTERFACE DPLB = plb_v34_0 | ||
2400 | BUS_INTERFACE IPLB = plb_v34_0 | ||
2401 | END | ||
2402 | |||
2403 | BEGIN opb_intc | ||
2404 | PARAMETER INSTANCE = opb_intc_0 | ||
2405 | PARAMETER HW_VER = 1.00.c | ||
2406 | PARAMETER C_BASEADDR = 0xD1000FC0 | ||
2407 | PARAMETER C_HIGHADDR = 0xD1000FDF | ||
2408 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2409 | END | ||
2410 | |||
2411 | BEGIN opb_uart16550 | ||
2412 | PARAMETER INSTANCE = opb_uart16550_0 | ||
2413 | PARAMETER HW_VER = 1.00.d | ||
2414 | PARAMETER C_BASEADDR = 0xa0000000 | ||
2415 | PARAMETER C_HIGHADDR = 0xa0001FFF | ||
2416 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2417 | END | ||
2418 | |||
2419 | BEGIN plb_v34 | ||
2420 | PARAMETER INSTANCE = plb_v34_0 | ||
2421 | PARAMETER HW_VER = 1.02.a | ||
2422 | END | ||
2423 | |||
2424 | BEGIN plb_bram_if_cntlr | ||
2425 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | ||
2426 | PARAMETER HW_VER = 1.00.b | ||
2427 | PARAMETER C_BASEADDR = 0xFFFF0000 | ||
2428 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | ||
2429 | BUS_INTERFACE SPLB = plb_v34_0 | ||
2430 | END | ||
2431 | |||
2432 | BEGIN plb2opb_bridge | ||
2433 | PARAMETER INSTANCE = plb2opb_bridge_0 | ||
2434 | PARAMETER HW_VER = 1.01.a | ||
2435 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | ||
2436 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | ||
2437 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | ||
2438 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | ||
2439 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | ||
2440 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | ||
2441 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | ||
2442 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | ||
2443 | BUS_INTERFACE SPLB = plb_v34_0 | ||
2444 | BUS_INTERFACE MOPB = opb_v20_0 | ||
2445 | END | ||
2446 | |||
2447 | Gives this device tree (some properties removed for clarity): | ||
2448 | |||
2449 | plb-v34-0 { | ||
2450 | #address-cells = <1>; | ||
2451 | #size-cells = <1>; | ||
2452 | device_type = "ibm,plb"; | ||
2453 | ranges; // 1:1 translation | ||
2454 | |||
2455 | plb-bram-if-cntrl-0@ffff0000 { | ||
2456 | reg = <ffff0000 10000>; | ||
2457 | } | ||
2458 | |||
2459 | opb-v20-0 { | ||
2460 | #address-cells = <1>; | ||
2461 | #size-cells = <1>; | ||
2462 | ranges = <20000000 20000000 20000000 | ||
2463 | 60000000 60000000 20000000 | ||
2464 | 80000000 80000000 40000000 | ||
2465 | c0000000 c0000000 20000000>; | ||
2466 | |||
2467 | opb-uart16550-0@a0000000 { | ||
2468 | reg = <a00000000 2000>; | ||
2469 | }; | ||
2470 | |||
2471 | opb-intc-0@d1000fc0 { | ||
2472 | reg = <d1000fc0 20>; | ||
2473 | }; | ||
2474 | }; | ||
2475 | }; | ||
2476 | |||
2477 | That covers the general approach to binding xilinx IP cores into the | ||
2478 | device tree. The following are bindings for specific devices: | ||
2479 | |||
2480 | i) Xilinx ML300 Framebuffer | ||
2481 | |||
2482 | Simple framebuffer device from the ML300 reference design (also on the | ||
2483 | ML403 reference design as well as others). | ||
2484 | |||
2485 | Optional properties: | ||
2486 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | ||
2487 | implementations use a different resolution. | ||
2488 | Default is <d#640 d#480> | ||
2489 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | ||
2490 | Default is <d#1024 d#480>. | ||
2491 | - rotate-display (empty) : rotate display 180 degrees. | ||
2492 | |||
2493 | ii) Xilinx SystemACE | ||
2494 | |||
2495 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | ||
2496 | bitstream stored on a CF card. It can also be used as a generic CF | ||
2497 | interface device. | ||
2498 | |||
2499 | Optional properties: | ||
2500 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | ||
2501 | |||
2502 | iii) Xilinx EMAC and Xilinx TEMAC | ||
2503 | |||
2504 | Xilinx Ethernet devices. In addition to general xilinx properties | ||
2505 | listed above, nodes for these devices should include a phy-handle | ||
2506 | property, and may include other common network device properties | ||
2507 | like local-mac-address. | ||
2508 | |||
2509 | iv) Xilinx Uartlite | ||
2510 | |||
2511 | Xilinx uartlite devices are simple fixed speed serial ports. | ||
2512 | |||
2513 | Requred properties: | ||
2514 | - current-speed : Baud rate of uartlite | ||
2515 | |||
2255 | More devices will be defined as this spec matures. | 2516 | More devices will be defined as this spec matures. |
2256 | 2517 | ||
2257 | VII - Specifying interrupt information for devices | 2518 | VII - Specifying interrupt information for devices |