diff options
author | Jon Hunter <jon-hunter@ti.com> | 2011-10-07 02:53:09 -0400 |
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committer | Paul Walmsley <paul@pwsan.com> | 2011-10-07 03:06:48 -0400 |
commit | cf2a82d7462e8c728260ee09e46c573fab2f89cf (patch) | |
tree | 5937a03d039c2713de65926c14a3b039001faa49 /Documentation/oops-tracing.txt | |
parent | 52a3a4d4610cfad536b8ac94b9a2f5ebfa51c06b (diff) |
ARM: OMAP4: clock: Add missing clock divider for OCP_ABE_ICLK
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the
parent clock of the AESS_FCLK is the ABE_FCLK...
ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK
The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which
determine their operational frequency. However, the dividers for
the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit,
which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to
0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2.
Similarly, when this bit is set to 1, the AESS_FCLK divider is 2
and the OCP_ABE_ICLK is 1.
The above relationship between the AESS_FCLK and OCP_ABE_ICLK
dividers ensure that the OCP_ABE_ICLK clock is always half the
frequency of the ABE_CLK...
OCP_ABE_ICLK = ABE_FCLK/2
The divider for the OCP_ABE_ICLK is currently missing so add a
divider that will ensure the OCP_ABE_ICLK frequency is always half
the ABE_FCLK frequency.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'Documentation/oops-tracing.txt')
0 files changed, 0 insertions, 0 deletions