diff options
| author | Andre Przywara <andre.przywara@amd.com> | 2010-03-24 12:46:42 -0400 |
|---|---|---|
| committer | Avi Kivity <avi@redhat.com> | 2010-04-20 05:59:31 -0400 |
| commit | 114be429c8cd44e57f312af2bbd6734e5a185b0d (patch) | |
| tree | 97ff3b4ea1e6f0f17a3ebe1cdd57f3c0682a789e /Documentation/misc-devices | |
| parent | d6a23895aa82353788a1cc5a1d9a1c963465463e (diff) | |
KVM: allow bit 10 to be cleared in MSR_IA32_MC4_CTL
There is a quirk for AMD K8 CPUs in many Linux kernels (see
arch/x86/kernel/cpu/mcheck/mce.c:__mcheck_cpu_apply_quirks()) that
clears bit 10 in that MCE related MSR. KVM can only cope with all
zeros or all ones, so it will inject a #GP into the guest, which
will let it panic.
So lets add a quirk to the quirk and ignore this single cleared bit.
This fixes -cpu kvm64 on all machines and -cpu host on K8 machines
with some guest Linux kernels.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'Documentation/misc-devices')
0 files changed, 0 insertions, 0 deletions