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authorPratyush Anand <pratyush.anand@st.com>2011-03-22 19:33:58 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-22 20:44:10 -0400
commitb9500546d5f85b56359657e1f78334db8de851fd (patch)
tree545f8152e70737587b06f940209cad6b5e273447 /Documentation/misc-devices/spear-pcie-gadget.txt
parent45bff2ea4285cac5b4438c65216e114d3619f123 (diff)
ST SPEAr: PCIE gadget suppport
This is a configurable gadget. can be configured by configfs interface. Any IP available at PCIE bus can be programmed to be used by host controller.It supoorts both INTX and MSI. By default, the gadget is configured for INTX and SYSRAM1 is mapped to BAR0 with size 0x1000 Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Cc: Randy Dunlap <randy.dunlap@oracle.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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1Spear PCIe Gadget Driver:
2
3Author
4=============
5Pratyush Anand (pratyush.anand@st.com)
6
7Location
8============
9driver/misc/spear13xx_pcie_gadget.c
10
11Supported Chip:
12===================
13SPEAr1300
14SPEAr1310
15
16Menuconfig option:
17==========================
18Device Drivers
19 Misc devices
20 PCIe gadget support for SPEAr13XX platform
21purpose
22===========
23This driver has several nodes which can be read/written by configfs interface.
24Its main purpose is to configure selected dual mode PCIe controller as device
25and then program its various registers to configure it as a particular device
26type. This driver can be used to show spear's PCIe device capability.
27
28Description of different nodes:
29=================================
30
31read behavior of nodes:
32------------------------------
33link :gives ltssm status.
34int_type :type of supported interrupt
35no_of_msi :zero if MSI is not enabled by host. A positive value is the
36 number of MSI vector granted.
37vendor_id :returns programmed vendor id (hex)
38device_id :returns programmed device id(hex)
39bar0_size: :returns size of bar0 in hex.
40bar0_address :returns address of bar0 mapped area in hex.
41bar0_rw_offset :returns offset of bar0 for which bar0_data will return value.
42bar0_data :returns data at bar0_rw_offset.
43
44write behavior of nodes:
45------------------------------
46link :write UP to enable ltsmm DOWN to disable
47int_type :write interrupt type to be configured and (int_type could be
48 INTA, MSI or NO_INT). Select MSI only when you have programmed
49 no_of_msi node.
50no_of_msi :number of MSI vector needed.
51inta :write 1 to assert INTA and 0 to de-assert.
52send_msi :write MSI vector to be sent.
53vendor_id :write vendor id(hex) to be programmed.
54device_id :write device id(hex) to be programmed.
55bar0_size :write size of bar0 in hex. default bar0 size is 1000 (hex)
56 bytes.
57bar0_address :write address of bar0 mapped area in hex. (default mapping of
58 bar0 is SYSRAM1(E0800000). Always program bar size before bar
59 address. Kernel might modify bar size and address for alignment, so
60 read back bar size and address after writing to cross check.
61bar0_rw_offset :write offset of bar0 for which bar0_data will write value.
62bar0_data :write data to be written at bar0_rw_offset.
63
64Node programming example
65===========================
66Program all PCIe registers in such a way that when this device is connected
67to the PCIe host, then host sees this device as 1MB RAM.
68#mount -t configfs none /Config
69For nth PCIe Device Controller
70# cd /config/pcie_gadget.n/
71Now you have all the nodes in this directory.
72program vendor id as 0x104a
73# echo 104A >> vendor_id
74
75program device id as 0xCD80
76# echo CD80 >> device_id
77
78program BAR0 size as 1MB
79# echo 100000 >> bar0_size
80
81check for programmed bar0 size
82# cat bar0_size
83
84Program BAR0 Address as DDR (0x2100000). This is the physical address of
85memory, which is to be made visible to PCIe host. Similarly any other peripheral
86can also be made visible to PCIe host. E.g., if you program base address of UART
87as BAR0 address then when this device will be connected to a host, it will be
88visible as UART.
89# echo 2100000 >> bar0_address
90
91program interrupt type : INTA
92# echo INTA >> int_type
93
94go for link up now.
95# echo UP >> link
96
97It will have to be insured that, once link up is done on gadget, then only host
98is initialized and start to search PCIe devices on its port.
99
100/*wait till link is up*/
101# cat link
102wait till it returns UP.
103
104To assert INTA
105# echo 1 >> inta
106
107To de-assert INTA
108# echo 0 >> inta
109
110if MSI is to be used as interrupt, program no of msi vector needed (say4)
111# echo 4 >> no_of_msi
112
113select MSI as interrupt type
114# echo MSI >> int_type
115
116go for link up now
117# echo UP >> link
118
119wait till link is up
120# cat link
121An application can repetitively read this node till link is found UP. It can
122sleep between two read.
123
124wait till msi is enabled
125# cat no_of_msi
126Should return 4 (number of requested MSI vector)
127
128to send msi vector 2
129# echo 2 >> send_msi
130#cd -