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authorIngo Molnar <mingo@kernel.org>2013-11-22 05:24:53 -0500
committerIngo Molnar <mingo@kernel.org>2013-11-22 05:46:12 -0500
commite0edc78f25c020dea66742c05a7fbcb2ff3df629 (patch)
tree613f944446f1011b8a6487f59b989e09833bbd9f /Documentation/memory-barriers.txt
parentb4789b8e6be3151a955ade74872822f30e8cd914 (diff)
Documentation/memory-barriers.txt: Fix a typo in the data dependency description
This typo has been there forever, it is 7.5 years old, looks like this section of our memory ordering documentation is a place where most eyes are glazed over already ;-) [ Also fix some stray spaces and stray tabs while at it, shrinking the file by 49 bytes. Visual output unchanged. ] Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-gncea9cb8igosblizfqMXrie@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt42
1 files changed, 21 insertions, 21 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index c8c42e64e953..020cccdbdd0c 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -500,7 +500,7 @@ odd-numbered bank is idle, one can see the new value of the pointer P (&B),
500but the old value of the variable B (2). 500but the old value of the variable B (2).
501 501
502 502
503Another example of where data dependency barriers might by required is where a 503Another example of where data dependency barriers might be required is where a
504number is read from memory and then used to calculate the index for an array 504number is read from memory and then used to calculate the index for an array
505access: 505access:
506 506
@@ -882,12 +882,12 @@ cache it for later use.
882 882
883Consider: 883Consider:
884 884
885 CPU 1 CPU 2 885 CPU 1 CPU 2
886 ======================= ======================= 886 ======================= =======================
887 LOAD B 887 LOAD B
888 DIVIDE } Divide instructions generally 888 DIVIDE } Divide instructions generally
889 DIVIDE } take a long time to perform 889 DIVIDE } take a long time to perform
890 LOAD A 890 LOAD A
891 891
892Which might appear as this: 892Which might appear as this:
893 893
@@ -910,13 +910,13 @@ Which might appear as this:
910Placing a read barrier or a data dependency barrier just before the second 910Placing a read barrier or a data dependency barrier just before the second
911load: 911load:
912 912
913 CPU 1 CPU 2 913 CPU 1 CPU 2
914 ======================= ======================= 914 ======================= =======================
915 LOAD B 915 LOAD B
916 DIVIDE 916 DIVIDE
917 DIVIDE 917 DIVIDE
918 <read barrier> 918 <read barrier>
919 LOAD A 919 LOAD A
920 920
921will force any value speculatively obtained to be reconsidered to an extent 921will force any value speculatively obtained to be reconsidered to an extent
922dependent on the type of barrier used. If there was no change made to the 922dependent on the type of barrier used. If there was no change made to the
@@ -1887,8 +1887,8 @@ functions:
1887 space should suffice for PCI. 1887 space should suffice for PCI.
1888 1888
1889 [*] NOTE! attempting to load from the same location as was written to may 1889 [*] NOTE! attempting to load from the same location as was written to may
1890 cause a malfunction - consider the 16550 Rx/Tx serial registers for 1890 cause a malfunction - consider the 16550 Rx/Tx serial registers for
1891 example. 1891 example.
1892 1892
1893 Used with prefetchable I/O memory, an mmiowb() barrier may be required to 1893 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
1894 force stores to be ordered. 1894 force stores to be ordered.
@@ -1955,19 +1955,19 @@ barriers for the most part act at the interface between the CPU and its cache
1955 : 1955 :
1956 +--------+ +--------+ : +--------+ +-----------+ 1956 +--------+ +--------+ : +--------+ +-----------+
1957 | | | | : | | | | +--------+ 1957 | | | | : | | | | +--------+
1958 | CPU | | Memory | : | CPU | | | | | 1958 | CPU | | Memory | : | CPU | | | | |
1959 | Core |--->| Access |----->| Cache |<-->| | | | 1959 | Core |--->| Access |----->| Cache |<-->| | | |
1960 | | | Queue | : | | | |--->| Memory | 1960 | | | Queue | : | | | |--->| Memory |
1961 | | | | : | | | | | | 1961 | | | | : | | | | | |
1962 +--------+ +--------+ : +--------+ | | | | 1962 +--------+ +--------+ : +--------+ | | | |
1963 : | Cache | +--------+ 1963 : | Cache | +--------+
1964 : | Coherency | 1964 : | Coherency |
1965 : | Mechanism | +--------+ 1965 : | Mechanism | +--------+
1966 +--------+ +--------+ : +--------+ | | | | 1966 +--------+ +--------+ : +--------+ | | | |
1967 | | | | : | | | | | | 1967 | | | | : | | | | | |
1968 | CPU | | Memory | : | CPU | | |--->| Device | 1968 | CPU | | Memory | : | CPU | | |--->| Device |
1969 | Core |--->| Access |----->| Cache |<-->| | | | 1969 | Core |--->| Access |----->| Cache |<-->| | | |
1970 | | | Queue | : | | | | | | 1970 | | | Queue | : | | | | | |
1971 | | | | : | | | | +--------+ 1971 | | | | : | | | | +--------+
1972 +--------+ +--------+ : +--------+ +-----------+ 1972 +--------+ +--------+ : +--------+ +-----------+
1973 : 1973 :
@@ -2090,7 +2090,7 @@ CPU's caches by some other cache event:
2090 p = &v; q = p; 2090 p = &v; q = p;
2091 <D:request p> 2091 <D:request p>
2092 <B:modify p=&v> <D:commit p=&v> 2092 <B:modify p=&v> <D:commit p=&v>
2093 <D:read p> 2093 <D:read p>
2094 x = *q; 2094 x = *q;
2095 <C:read *q> Reads from v before v updated in cache 2095 <C:read *q> Reads from v before v updated in cache
2096 <C:unbusy> 2096 <C:unbusy>
@@ -2115,7 +2115,7 @@ queue before processing any further requests:
2115 p = &v; q = p; 2115 p = &v; q = p;
2116 <D:request p> 2116 <D:request p>
2117 <B:modify p=&v> <D:commit p=&v> 2117 <B:modify p=&v> <D:commit p=&v>
2118 <D:read p> 2118 <D:read p>
2119 smp_read_barrier_depends() 2119 smp_read_barrier_depends()
2120 <C:unbusy> 2120 <C:unbusy>
2121 <C:commit v=2> 2121 <C:commit v=2>