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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-03 19:35:11 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-03 19:35:11 -0400
commit708e16892e1646594a29eaa7ac7b209b600b9fd2 (patch)
treefe7c31bc0edef84eb1075c7e195340047d6aaa17 /Documentation/memory-barriers.txt
parentf3c87a8999c28f2948ebd407574f7e9fb5c577b2 (diff)
parenta847825970e741e20a09c659978baa34016b63bc (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (39 commits) Add missing maintainer countries in CREDITS Fix bytes <-> kilobytes typo in Kconfig for ramdisk fix a typo in Documentation/pi-futex.txt BUG_ON conversion for fs/xfs/ BUG_ON() conversion in fs/nfsd/ BUG_ON conversion for fs/reiserfs BUG_ON cleanups in arch/i386 BUG_ON cleanup in drivers/net/tokenring/ BUG_ON cleanup for drivers/md/ kerneldoc-typo in led-class.c debugfs: spelling fix rcutorture: Fix incorrect description of default for nreaders parameter parport: Remove space in function calls Michal Wronski: update contact info Spelling fix: "control" instead of "cotrol" reboot parameter in Documentation/kernel-parameters.txt Fix copy&waste bug in comment in scripts/kernel-doc remove duplicate "until" from kernel/workqueue.c ite_gpio fix tabbage fix file specification in comments ... Fixed trivial path conflicts due to removed files: arch/mips/dec/boot/decstation.c, drivers/char/ite_gpio.c
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 46b9b389df35..994355b0cd19 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -670,7 +670,7 @@ effectively random order, despite the write barrier issued by CPU 1:
670 670
671 671
672In the above example, CPU 2 perceives that B is 7, despite the load of *C 672In the above example, CPU 2 perceives that B is 7, despite the load of *C
673(which would be B) coming after the the LOAD of C. 673(which would be B) coming after the LOAD of C.
674 674
675If, however, a data dependency barrier were to be placed between the load of C 675If, however, a data dependency barrier were to be placed between the load of C
676and the load of *C (ie: B) on CPU 2: 676and the load of *C (ie: B) on CPU 2:
@@ -1915,7 +1915,7 @@ Whilst most CPUs do imply a data dependency barrier on the read when a memory
1915access depends on a read, not all do, so it may not be relied on. 1915access depends on a read, not all do, so it may not be relied on.
1916 1916
1917Other CPUs may also have split caches, but must coordinate between the various 1917Other CPUs may also have split caches, but must coordinate between the various
1918cachelets for normal memory accesss. The semantics of the Alpha removes the 1918cachelets for normal memory accesses. The semantics of the Alpha removes the
1919need for coordination in absence of memory barriers. 1919need for coordination in absence of memory barriers.
1920 1920
1921 1921