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authorWill Schmidt <will_schmidt@vnet.ibm.com>2010-09-28 11:33:12 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-11-28 23:48:18 -0500
commit4e89a2d8e2d5ab33d73b76f16c10fdf515faabef (patch)
tree0300f10bfc192f9e9d8deed50ae857512760f8ab /Documentation/kernel-parameters.txt
parent475fc7c011ace79258c07d981d348a15614e0573 (diff)
powerpc/pseries: Add kernel parameter to disable batched hcalls
This introduces a pair of kernel parameters that can be used to disable the MULTITCE and BULK_REMOVE h-calls. By default, those hcalls are enabled, active, and good for throughput and performance. The ability to disable them will be useful for some of the PREEMPT_RT related investigation and work occurring on Power. Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com> cc: Olof Johansson <olof@lixom.net> cc: Anton Blanchard <anton@samba.org> cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'Documentation/kernel-parameters.txt')
-rw-r--r--Documentation/kernel-parameters.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index cdd2a6e8a3b7..69bb6a9c871a 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -403,6 +403,10 @@ and is between 256 and 4096 characters. It is defined in the file
403 bttv.pll= See Documentation/video4linux/bttv/Insmod-options 403 bttv.pll= See Documentation/video4linux/bttv/Insmod-options
404 bttv.tuner= and Documentation/video4linux/bttv/CARDLIST 404 bttv.tuner= and Documentation/video4linux/bttv/CARDLIST
405 405
406 bulk_remove=off [PPC] This parameter disables the use of the pSeries
407 firmware feature for flushing multiple hpte entries
408 at a time.
409
406 c101= [NET] Moxa C101 synchronous serial card 410 c101= [NET] Moxa C101 synchronous serial card
407 411
408 cachesize= [BUGS=X86-32] Override level 2 CPU cache size detection. 412 cachesize= [BUGS=X86-32] Override level 2 CPU cache size detection.
@@ -1490,6 +1494,10 @@ and is between 256 and 4096 characters. It is defined in the file
1490 mtdparts= [MTD] 1494 mtdparts= [MTD]
1491 See drivers/mtd/cmdlinepart.c. 1495 See drivers/mtd/cmdlinepart.c.
1492 1496
1497 multitce=off [PPC] This parameter disables the use of the pSeries
1498 firmware feature for updating multiple TCE entries
1499 at a time.
1500
1493 onenand.bdry= [HW,MTD] Flex-OneNAND Boundary Configuration 1501 onenand.bdry= [HW,MTD] Flex-OneNAND Boundary Configuration
1494 1502
1495 Format: [die0_boundary][,die0_lock][,die1_boundary][,die1_lock] 1503 Format: [die0_boundary][,die0_lock][,die1_boundary][,die1_lock]