Fix typos in /Documentation : Misc

This patch fixes typos in various Documentation txts. The patch addresses some
misc words.

Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Acked-by: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: Adrian Bunk <bunk@stusta.de>

1 files changed, 5 insertions, 5 deletions

diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
index 50f4eddf899c..4b3d6710c504 100644
--- a/Documentation/kbuild/makefiles.txt
+++ b/Documentation/kbuild/makefiles.txt
@@ -227,9 +227,9 @@ more details, with real examples.
         be included in a library, lib.a.
         All objects listed with lib-y are combined in a single
         library for that directory.
-        Objects that are listed in obj-y and additionaly listed in
-        lib-y will not be included in the library, since they will anyway
-        be accessible.
+        Objects that are listed in obj-y and additionally listed in
+        lib-y will not be included in the library, since they will
+        be accessible anyway.
         For consistency, objects listed in lib-m will be included in lib.a.
 
         Note that the same kbuild makefile may list files to be built-in
@@ -535,7 +535,7 @@ Both possibilities are described in the following.
         Host programs can be made up based on composite objects.
         The syntax used to define composite objects for host programs is
         similar to the syntax used for kernel objects.
-        $(<executeable>-objs) lists all objects used to link the final
+        $(<executable>-objs) lists all objects used to link the final
         executable.
 
         Example:
@@ -1022,7 +1022,7 @@ When kbuild executes, the following steps are followed (roughly):
         In this example, there are two possible targets, requiring different
         options to the linker. The linker options are specified using the
         LDFLAGS_$@ syntax - one for each potential target.
-        $(targets) are assinged all potential targets, by which kbuild knows
+        $(targets) are assigned all potential targets, by which kbuild knows
         the targets and will:
                 1) check for commandline changes
                 2) delete target during make clean