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authorOleg Ryjkov <olegr@google.com>2007-07-12 08:12:31 -0400
committerJean Delvare <khali@hyperion.delvare>2007-07-12 08:12:31 -0400
commit7edcb9abb594a8f3b4ca756e03d01c870aeae127 (patch)
tree1a58c21abdb71a2ec146225e0d226103926dbbd7 /Documentation/i2c/busses
parentca8b9e32a11a7cbfecbef00c8451a79fe1af392e (diff)
i2c-i801: Use the internal 32-byte buffer on ICH4+
Add an ability to utilize the internal SRAM buffer on ICH4 and newer host controllers to speed up execution of block operations. I've split the code so that it is more clear which block transaction is performed. First of all the host controller's type is identified. isich4 is set when we think that the controller has the internal buffer. Then, before every block transaction, if isich4 is set, we attempt to enable the E32B bit in SMBAUXCTL register. Signed-off-by: Oleg Ryjkov <olegr@google.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
Diffstat (limited to 'Documentation/i2c/busses')
-rw-r--r--Documentation/i2c/busses/i2c-i8014
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index c34f0db78a30..fe6406f2f9a6 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -5,8 +5,8 @@ Supported adapters:
5 '810' and '810E' chipsets) 5 '810' and '810E' chipsets)
6 * Intel 82801BA (ICH2 - part of the '815E' chipset) 6 * Intel 82801BA (ICH2 - part of the '815E' chipset)
7 * Intel 82801CA/CAM (ICH3) 7 * Intel 82801CA/CAM (ICH3)
8 * Intel 82801DB (ICH4) (HW PEC supported, 32 byte buffer not supported) 8 * Intel 82801DB (ICH4) (HW PEC supported)
9 * Intel 82801EB/ER (ICH5) (HW PEC supported, 32 byte buffer not supported) 9 * Intel 82801EB/ER (ICH5) (HW PEC supported)
10 * Intel 6300ESB 10 * Intel 6300ESB
11 * Intel 82801FB/FR/FW/FRW (ICH6) 11 * Intel 82801FB/FR/FW/FRW (ICH6)
12 * Intel 82801G (ICH7) 12 * Intel 82801G (ICH7)