diff options
author | Anton Altaparmakov <aia21@cantab.net> | 2005-10-30 16:00:04 -0500 |
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committer | Anton Altaparmakov <aia21@cantab.net> | 2005-10-30 16:00:04 -0500 |
commit | 07b188ab773e183871e57b33ae37bf635c9f12ba (patch) | |
tree | 311df8a0dd12fb7bd3e9b5b1a5ca500f0428d679 /Documentation/hwmon/lm90 | |
parent | 47c564e10f219f867bdb49225972749a43485a47 (diff) | |
parent | 9f75e1eff3edb2bb07349b94c28f4f2a6c66ca43 (diff) |
Merge branch 'master' of /usr/src/ntfs-2.6/
Diffstat (limited to 'Documentation/hwmon/lm90')
-rw-r--r-- | Documentation/hwmon/lm90 | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/Documentation/hwmon/lm90 b/Documentation/hwmon/lm90 index 2c4cf39471f4..438cb24cee5b 100644 --- a/Documentation/hwmon/lm90 +++ b/Documentation/hwmon/lm90 | |||
@@ -24,14 +24,14 @@ Supported chips: | |||
24 | http://www.national.com/pf/LM/LM86.html | 24 | http://www.national.com/pf/LM/LM86.html |
25 | * Analog Devices ADM1032 | 25 | * Analog Devices ADM1032 |
26 | Prefix: 'adm1032' | 26 | Prefix: 'adm1032' |
27 | Addresses scanned: I2C 0x4c | 27 | Addresses scanned: I2C 0x4c and 0x4d |
28 | Datasheet: Publicly available at the Analog Devices website | 28 | Datasheet: Publicly available at the Analog Devices website |
29 | http://products.analog.com/products/info.asp?product=ADM1032 | 29 | http://www.analog.com/en/prod/0,2877,ADM1032,00.html |
30 | * Analog Devices ADT7461 | 30 | * Analog Devices ADT7461 |
31 | Prefix: 'adt7461' | 31 | Prefix: 'adt7461' |
32 | Addresses scanned: I2C 0x4c | 32 | Addresses scanned: I2C 0x4c and 0x4d |
33 | Datasheet: Publicly available at the Analog Devices website | 33 | Datasheet: Publicly available at the Analog Devices website |
34 | http://products.analog.com/products/info.asp?product=ADT7461 | 34 | http://www.analog.com/en/prod/0,2877,ADT7461,00.html |
35 | Note: Only if in ADM1032 compatibility mode | 35 | Note: Only if in ADM1032 compatibility mode |
36 | * Maxim MAX6657 | 36 | * Maxim MAX6657 |
37 | Prefix: 'max6657' | 37 | Prefix: 'max6657' |
@@ -71,8 +71,8 @@ increased resolution of the remote temperature measurement. | |||
71 | 71 | ||
72 | The different chipsets of the family are not strictly identical, although | 72 | The different chipsets of the family are not strictly identical, although |
73 | very similar. This driver doesn't handle any specific feature for now, | 73 | very similar. This driver doesn't handle any specific feature for now, |
74 | but could if there ever was a need for it. For reference, here comes a | 74 | with the exception of SMBus PEC. For reference, here comes a non-exhaustive |
75 | non-exhaustive list of specific features: | 75 | list of specific features: |
76 | 76 | ||
77 | LM90: | 77 | LM90: |
78 | * Filter and alert configuration register at 0xBF. | 78 | * Filter and alert configuration register at 0xBF. |
@@ -91,6 +91,7 @@ ADM1032: | |||
91 | * Conversion averaging. | 91 | * Conversion averaging. |
92 | * Up to 64 conversions/s. | 92 | * Up to 64 conversions/s. |
93 | * ALERT is triggered by open remote sensor. | 93 | * ALERT is triggered by open remote sensor. |
94 | * SMBus PEC support for Write Byte and Receive Byte transactions. | ||
94 | 95 | ||
95 | ADT7461 | 96 | ADT7461 |
96 | * Extended temperature range (breaks compatibility) | 97 | * Extended temperature range (breaks compatibility) |
@@ -119,3 +120,37 @@ The lm90 driver will not update its values more frequently than every | |||
119 | other second; reading them more often will do no harm, but will return | 120 | other second; reading them more often will do no harm, but will return |
120 | 'old' values. | 121 | 'old' values. |
121 | 122 | ||
123 | PEC Support | ||
124 | ----------- | ||
125 | |||
126 | The ADM1032 is the only chip of the family which supports PEC. It does | ||
127 | not support PEC on all transactions though, so some care must be taken. | ||
128 | |||
129 | When reading a register value, the PEC byte is computed and sent by the | ||
130 | ADM1032 chip. However, in the case of a combined transaction (SMBus Read | ||
131 | Byte), the ADM1032 computes the CRC value over only the second half of | ||
132 | the message rather than its entirety, because it thinks the first half | ||
133 | of the message belongs to a different transaction. As a result, the CRC | ||
134 | value differs from what the SMBus master expects, and all reads fail. | ||
135 | |||
136 | For this reason, the lm90 driver will enable PEC for the ADM1032 only if | ||
137 | the bus supports the SMBus Send Byte and Receive Byte transaction types. | ||
138 | These transactions will be used to read register values, instead of | ||
139 | SMBus Read Byte, and PEC will work properly. | ||
140 | |||
141 | Additionally, the ADM1032 doesn't support SMBus Send Byte with PEC. | ||
142 | Instead, it will try to write the PEC value to the register (because the | ||
143 | SMBus Send Byte transaction with PEC is similar to a Write Byte transaction | ||
144 | without PEC), which is not what we want. Thus, PEC is explicitely disabled | ||
145 | on SMBus Send Byte transactions in the lm90 driver. | ||
146 | |||
147 | PEC on byte data transactions represents a significant increase in bandwidth | ||
148 | usage (+33% for writes, +25% for reads) in normal conditions. With the need | ||
149 | to use two SMBus transaction for reads, this overhead jumps to +50%. Worse, | ||
150 | two transactions will typically mean twice as much delay waiting for | ||
151 | transaction completion, effectively doubling the register cache refresh time. | ||
152 | I guess reliability comes at a price, but it's quite expensive this time. | ||
153 | |||
154 | So, as not everyone might enjoy the slowdown, PEC can be disabled through | ||
155 | sysfs. Just write 0 to the "pec" file and PEC will be disabled. Write 1 | ||
156 | to that file to enable PEC again. | ||