Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...

10 files changed, 388 insertions, 3 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 14d5c2af26f4..c6bf8a6c8f52 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable.
   spi0_isp_sclk       380     Exynos4x12
   spi1_isp_sclk       381     Exynos4x12
   uart_isp_sclk       382     Exynos4x12
+  tmu_apbif           383
 
                 [Mux Clocks]
 
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a6276adf7..24765c146e31 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -59,6 +59,9 @@ clock which they consume.
   sclk_spi0             154
   sclk_spi1             155
   sclk_spi2             156
+  div_i2s1              157
+  div_i2s2              158
+  sclk_hdmiphy          159
 
 
    [Peripheral Clock Gates]
@@ -154,7 +157,16 @@ clock which they consume.
   dsim0                 341
   dp                    342
   mixer                 343
-  hdmi                  345
+  hdmi                  344
+  g2d                   345
+
+
+   [Clock Muxes]
+
+  Clock                 ID
+  ----------------------------
+  mout_hdmi             1024
+
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1bff51..32aa34ecad36 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
   sclk_pwm              155
   sclk_gscl_wa          156
   sclk_gscl_wb          157
+  sclk_hdmiphy          158
 
    [Peripheral Clock Gates]
 
@@ -179,6 +180,17 @@ clock which they consume.
   fimc_lite3            495
   aclk_g3d              500
   g3d                   501
+  smmu_mixer            502
+
+  Mux                   ID
+  ----------------------------
+
+  mout_hdmi             640
+
+  Divider               ID
+  ----------------------------
+
+  dout_pixel            768
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
new file mode 100644
index 000000000000..fa171dc4bd3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
@@ -0,0 +1,77 @@
+* Samsung S3C64xx Clock Controller
+
+The S3C64xx clock controller generates and supplies clock to various controllers
+within the SoC. The clock binding described here is applicable to all SoCs in
+the S3C64xx family.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
+  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular S3C64xx SoC and this is specified where applicable.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
+tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "fin_pll" - PLL input clock (xtal/extclk) - required,
+ - "xusbxti" - USB xtal - required,
+ - "iiscdclk0" - I2S0 codec clock - optional,
+ - "iiscdclk1" - I2S1 codec clock - optional,
+ - "iiscdclk2" - I2S2 codec clock - optional,
+ - "pcmcdclk0" - PCM0 codec clock - optional,
+ - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
+
+Example: Clock controller node:
+
+        clock: clock-controller@7e00f000 {
+                compatible = "samsung,s3c6410-clock";
+                reg = <0x7e00f000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+Example: Required external clocks:
+
+        fin_pll: clock-fin-pll {
+                compatible = "fixed-clock";
+                clock-output-names = "fin_pll";
+                clock-frequency = <12000000>;
+                #clock-cells = <0>;
+        };
+
+        xusbxti: clock-xusbxti {
+                compatible = "fixed-clock";
+                clock-output-names = "xusbxti";
+                clock-frequency = <48000000>;
+                #clock-cells = <0>;
+        };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller (refer to the standard clock bindings for information about
+  "clocks" and "clock-names" properties):
+
+                uart0: serial@7f005000 {
+                        compatible = "samsung,s3c6400-uart";
+                        reg = <0x7f005000 0x100>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <5>;
+                        clock-names = "uart", "clk_uart_baud2",
+                                        "clk_uart_baud3";
+                        clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
+                                        <&clock SCLK_UART>;
+                        status = "disabled";
+                };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d495521a79d2..00a5c26454eb 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -8,19 +8,31 @@ Required properties:
 - compatible : shall be one of the following:
         "allwinner,sun4i-osc-clk" - for a gatable oscillator
         "allwinner,sun4i-pll1-clk" - for the main PLL clock
+        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
         "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-axi-clk" - for the AXI clock
         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-ahb-clk" - for the AHB clock
         "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
+        "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
+        "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
+        "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+        "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
         "allwinner,sun4i-apb0-clk" - for the APB0 clock
         "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
+        "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
+        "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
         "allwinner,sun4i-apb1-clk" - for the APB1 clock
         "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
         "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
+        "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
+        "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
+        "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
+        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
new file mode 100644
index 000000000000..d24279fe1429
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
@@ -0,0 +1,75 @@
+Gate clock outputs
+------------------
+
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+    DRAM                                        0
+
+  * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
+
+    USB0                                        0
+    EHCI0                                       1
+    OHCI0                                       2
+
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+
+    NAND                                        13
+    SDRAM                                       14
+
+    EMAC                                        17
+    TS                                          18
+
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+
+    GPS                                         26
+
+    HSTIMER                                     28
+
+    VE                                          32
+
+    TVE                                         34
+
+    LCD                                         36
+
+    CSI                                         40
+
+    HDMI                                        43
+    DE_BE                                       44
+
+    DE_FE                                       46
+
+    IEP                                         51
+    MALI400                                     52
+
+  * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
+
+    CODEC                                       0
+
+    IIS                                         3
+
+    PIO                                         5
+    IR                                          6
+
+    KEYPAD                                      10
+
+  * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
new file mode 100644
index 000000000000..fe44932b5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
@@ -0,0 +1,83 @@
+Gate clock outputs
+------------------
+
+  * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk")
+
+    MIPI DSI                                    1
+
+    SS                                          5
+    DMA                                         6
+
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    MMC3                                        11
+
+    NAND1                                       12
+    NAND0                                       13
+    SDRAM                                       14
+
+    GMAC                                        17
+    TS                                          18
+    HSTIMER                                     19
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    SPI3                                        23
+    USB_OTG                                     24
+
+    EHCI0                                       26
+    EHCI1                                       27
+
+    OHCI0                                       29
+    OHCI1                                       30
+    OHCI2                                       31
+    VE                                          32
+
+    LCD0                                        36
+    LCD1                                        37
+
+    CSI                                         40
+
+    HDMI                                        43
+    DE_BE0                                      44
+    DE_BE1                                      45
+    DE_FE1                                      46
+    DE_FE1                                      47
+
+    MP                                          50
+
+    GPU                                         52
+
+    DEU0                                        55
+    DEU1                                        56
+    DRC0                                        57
+    DRC1                                        58
+
+  * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk")
+
+    CODEC                                       0
+
+    DIGITAL MIC                                 4
+    PIO                                         5
+
+    DAUDIO0                                     12
+    DAUDIO1                                     13
+
+  * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    I2C3                                        3
+
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+    UART4                                       20
+    UART5                                       21
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
new file mode 100644
index 000000000000..357f4fdc02ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
@@ -0,0 +1,98 @@
+Gate clock outputs
+------------------
+
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+    DRAM                                        0
+
+  * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk")
+
+    USB0                                        0
+    EHCI0                                       1
+    OHCI0                                       2
+    EHCI1                                       3
+    OHCI1                                       4
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    MMC3                                        11
+    MS                                          12
+    NAND                                        13
+    SDRAM                                       14
+
+    ACE                                         16
+    EMAC                                        17
+    TS                                          18
+
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    SPI3                                        23
+
+    SATA                                        25
+
+    HSTIMER                                     28
+
+    VE                                          32
+    TVD                                         33
+    TVE0                                        34
+    TVE1                                        35
+    LCD0                                        36
+    LCD1                                        37
+
+    CSI0                                        40
+    CSI1                                        41
+
+    HDMI1                                       42
+    HDMI0                                       43
+    DE_BE0                                      44
+    DE_BE1                                      45
+    DE_FE1                                      46
+    DE_FE1                                      47
+
+    GMAC                                        49
+    MP                                          50
+
+    MALI400                                     52
+
+  * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk")
+
+    CODEC                                       0
+    SPDIF                                       1
+    AC97                                        2
+    IIS0                                        3
+    IIS1                                        4
+    PIO                                         5
+    IR0                                         6
+    IR1                                         7
+    IIS2                                        8
+
+    KEYPAD                                      10
+
+  * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    I2C3                                        3
+    CAN                                         4
+    SCR                                         5
+    PS20                                        6
+    PS21                                        7
+
+    I2C4                                        15
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+    UART4                                       20
+    UART5                                       21
+    UART6                                       22
+    UART7                                       23
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 3f454ffc654a..c4f358dafdaa 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -11,8 +11,11 @@ Required properties:
 
   - interrupts : G2D interrupt number to the CPU.
   - clocks : from common clock binding: handle to G2D clocks.
-  - clock-names : from common clock binding: must contain "sclk_fimg2d" and
-                  "fimg2d", corresponding to entries in the clocks property.
+  - clock-names : names of clocks listed in clocks property, in the same
+                  order, depending on SoC type:
+                  - for S5PV210 and Exynos4 based SoCs: "fimg2d" and
+                    "sclk_fimg2d"
+                  - for Exynos5250 SoC: "fimg2d".
 
 Example:
         g2d@12800000 {
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
index 4caa1a78863e..d61fccd40bad 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
@@ -19,6 +19,16 @@ Required properties:
 - reg: base address and size of register area
 - interrupts: list of timer interrupts (one interrupt per timer, starting at
   timer 0)
+- clock-names: should contain all following required clock names:
+    - "timers" - PWM base clock used to generate PWM signals,
+  and any subset of following optional clock names:
+    - "pwm-tclk0" - first external PWM clock source,
+    - "pwm-tclk1" - second external PWM clock source.
+  Note that not all IP variants allow using all external clock sources.
+  Refer to SoC documentation to learn which clock source configurations
+  are available.
+- clocks: should contain clock specifiers of all clocks, which input names
+  have been specified in clock-names property, in same order.
 - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
   the cells format. The only third cell flag supported by this binding is
   PWM_POLARITY_INVERTED.
@@ -34,6 +44,8 @@ Example:
                 reg = <0x7f006000 0x1000>;
                 interrupt-parent = <&vic0>;
                 interrupts = <23>, <24>, <25>, <27>, <28>;
+                clocks = <&clock 67>;
+                clock-names = "timers";
                 samsung,pwm-outputs = <0>, <1>;
                 #pwm-cells = <3>;
         }