Merge tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late

Pull "The i.MX device tree updates for 4.1" from Shawn Guo:

 - Convert GPC controller to use stacked interrupt domains
 - Add power domain descriptions for i.MX6 platforms
 - Improve i.MX25 pin function defines
 - Disable PWM devices in <soc>.dtsi by default and enable it at board
   level dts where the device is actually available.
 - Define labels for SNVS RTC device to ease the board description,
   where an external RTC is available.
 - Add dr_mode host setting to all i.MX host-only USB instances
 - Support Miscellaneous System Control Module (MSCM) for VF610
 - Add initial i.MX6SL WaRP Board support
 - Add i.MX6SX SDB revision B board support
 - A bunch of imx28-apf28dev board updates, including gpio polarity
   correction and CAN, AUART device support.
 - SolidRun iMX6 platform updates: dual-license of GPLv2/X11, PWM
   setup, PCF8523 RTC, GPIO key and SGTL5000 audio support.
 - A number of random device additions for boards: SPI and CAN for
   vf-colibri, MAX7310 GPIO expander for imx6qdl-sabreauto and LCD
   support for imx25-pdk.

Note: Branch imx/cleanup was merged as the base to solve conflict on
imx25 iomux header.  Branch imx/soc was merged as the base to solve
conflict on arch/arm/mach-imx/gpc.c.  And Jason Cooper's irqchip/vybrid
branch was pulled into the base as a run-time dependency.

* tag 'imx-dt-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
  ARM: dts: hummingboard: add sgtl5000 support for Hummingboard Pro
  ARM: dts: imx25-pinfunc: Add several pinfunctions
  ARM: dts: vf610: fix missing irqs
  ARM: dts: cubox: Map gpio-keys to gpio3 8
  ARM: dts: hummingboard: Setup pwm lines
  ARM: dts: hummingboard: enable PCF8523 RTC support
  ARM: dts: Re-license SolidRun iMX6 platform DT GPL v2/X11
  ARM: dts: imx28: add alternative pinmuxing for spi3
  ARM: dts: imx6sx: Add label snvs_rtc
  ARM: dts: imx6sl: Add label snvs_rtc
  ARM: imx6: Warn when an old DT is detected
  ARM: imx6: Allow GPC interrupts affinity to be changed
  ARM: imx6qdl-sabreauto.dtsi: add max7310 support
  ARM: dts: imx6sl-warp: Add BCM4330 support
  ARM: dts: imx28-apf28dev: add wakeup function to user button
  ARM: dts: imx28-apf28dev: fix user button polarity
  ARM: dts: imx25-pinfunc: remove input values for pinfuncs without input register
  ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
  ARM: dts: imx6sl-warp: Pass 'bus-width' property
  ARM: dts: imx6qdl: disable PWMs by default
  ...

3 files changed, 106 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
new file mode 100644
index 000000000000..44aa3c451ccf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
@@ -0,0 +1,14 @@
+Freescale Vybrid Miscellaneous System Control - CPU Configuration
+
+The MSCM IP contains multiple sub modules, this binding describes the first
+block of registers which contains CPU configuration information.
+
+Required properties:
+- compatible:   "fsl,vf610-mscm-cpucfg", "syscon"
+- reg:          the register range of the MSCM CPU configuration registers
+
+Example:
+        mscm_cpucfg: cpucfg@40001000 {
+                compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+                reg = <0x40001000 0x800>;
+        }
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
new file mode 100644
index 000000000000..669808b2af49
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -0,0 +1,33 @@
+Freescale Vybrid Miscellaneous System Control - Interrupt Router
+
+The MSCM IP contains multiple sub modules, this binding describes the second
+block of registers which control the interrupt router. The interrupt router
+allows to configure the recipient of each peripheral interrupt. Furthermore
+it controls the directed processor interrupts. The module is available in all
+Vybrid SoC's but is only really useful in dual core configurations (VF6xx
+which comes with a Cortex-A5/Cortex-M4 combination).
+
+Required properties:
+- compatible:           "fsl,vf610-mscm-ir"
+- reg:                  the register range of the MSCM Interrupt Router
+- fsl,cpucfg:           The handle to the MSCM CPU configuration node, required
+                        to get the current CPU ID
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells:     Two cells, interrupt number and cells.
+                        The hardware interrupt number according to interrupt
+                        assignment of the interrupt router is required.
+                        Flags get passed only when using GIC as parent. Flags
+                        encoding as documented by the GIC bindings.
+- interrupt-parent:     Should be the phandle for the interrupt controller of
+                        the CPU the device tree is intended to be used on. This
+                        is either the node of the GIC or NVIC controller.
+
+Example:
+        mscm_ir: interrupt-controller@40001800 {
+                compatible = "fsl,vf610-mscm-ir";
+                reg = <0x40001800 0x400>;
+                fsl,cpucfg = <&mscm_cpucfg>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                interrupt-parent = <&intc>;
+        }
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
new file mode 100644
index 000000000000..65cc0345747d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
@@ -0,0 +1,59 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+          to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+        gpc: gpc@020dc000 {
+                compatible = "fsl,imx6q-gpc";
+                reg = <0x020dc000 0x4000>;
+                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                pu-supply = <&reg_pu>;
+                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                         <&clks IMX6QDL_CLK_VPU_AXI>;
+                #power-domain-cells = <1>;
+        };
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+        vpu: vpu@02040000 {
+                reg = <0x02040000 0x3c000>;
+                /* ... */
+                power-domains = <&gpc 1>;
+                /* ... */
+        };
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN     0
+PU_DOMAIN      1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2