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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 17:08:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 17:08:46 -0400
commit7bf97e1d5a94b6a71815771bb9452fc2c022c966 (patch)
treef89082dbd33a51a79c9a9c0dddb29e2b11b8207e /Documentation/devicetree
parent30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f (diff)
parentc77c8a6fd3d57b586ff5ecb5ab5b32ca4f54fe75 (diff)
Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull GPIO changes for v3.4 from Grant Likely: "Primarily gpio device driver changes with some minor side effects under arch/arm and arch/x86. Also includes a few core changes such as explicitly supporting (electrical) open source and open drain outputs and some help for parsing gpio devicetree properties." Fix up context conflict due to Laxman Dewangan adding sleep control for the tps65910 driver separately for gpio's and regulators. * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: (34 commits) gpio/ep93xx: Remove unused inline function and useless pr_err message gpio/sodaville: Mark broken due to core irqdomain migration gpio/omap: fix redundant decoding of gpio offset gpio/omap: fix incorrect update to context.irqenable1 gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_* gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg gpio/omap: fix _set_gpio_irqenable implementation gpio/omap: fix trigger type to unsigned gpio/omap: fix wakeup_en register update in _set_gpio_wakeup() gpio: tegra: tegra_gpio_config shouldn't be __init gpio/davinci: fix enabling unbanked GPIO IRQs gpio/davinci: fix oops on unbanked gpio irq request gpio/omap: Fix section warning for omap_mpuio_alloc_gc() ARM: tegra: export tegra_gpio_{en,dis}able gpio/gpio-stmpe: Fix the value returned by _get_value routine Documentation/gpio.txt: Explain expected pinctrl interaction GPIO: LPC32xx: Add output reading to GPO P3 GPIO: LPC32xx: Fix missing bit selection mask gpio/omap: fix wakeups on level-triggered GPIOs gpio/omap: Fix IRQ handling for SPARSE_IRQ ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-omap.txt36
-rw-r--r--Documentation/devicetree/bindings/gpio/sodaville.txt48
2 files changed, 84 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt
new file mode 100644
index 000000000000..bff51a2fee1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-omap.txt
@@ -0,0 +1,36 @@
1OMAP GPIO controller bindings
2
3Required properties:
4- compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8- #gpio-cells : Should be two.
9 - first cell is the pin number
10 - second cell is used to specify optional parameters (unused)
11- gpio-controller : Marks the device node as a GPIO controller.
12- #interrupt-cells : Should be 2.
13- interrupt-controller: Mark the device node as an interrupt controller
14 The first cell is the GPIO number.
15 The second cell is used to specify flags:
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
20 8 = active low level-sensitive.
21
22OMAP specific properties:
23- ti,hwmods: Name of the hwmod associated to the GPIO:
24 "gpio<X>", <X> being the 1-based instance number from the HW spec
25
26
27Example:
28
29gpio4: gpio4 {
30 compatible = "ti,omap4-gpio";
31 ti,hwmods = "gpio4";
32 #gpio-cells = <2>;
33 gpio-controller;
34 #interrupt-cells = <2>;
35 interrupt-controller;
36};
diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt
new file mode 100644
index 000000000000..563eff22b975
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/sodaville.txt
@@ -0,0 +1,48 @@
1GPIO controller on CE4100 / Sodaville SoCs
2==========================================
3
4The bindings for CE4100's GPIO controller match the generic description
5which is covered by the gpio.txt file in this folder.
6
7The only additional property is the intel,muxctl property which holds the
8value which is written into the MUXCNTL register.
9
10There is no compatible property for now because the driver is probed via
11PCI id (vendor 0x8086 device 0x2e67).
12
13The interrupt specifier consists of two cells encoded as follows:
14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
18
19Example of the GPIO device and one user:
20
21 pcigpio: gpio@b,1 {
22 /* two cells for GPIO and interrupt */
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
25 compatible = "pci8086,2e67.2",
26 "pci8086,2e67",
27 "pciclassff0000",
28 "pciclassff00";
29
30 reg = <0x15900 0x0 0x0 0x0 0x0>;
31 /* Interrupt line of the gpio device */
32 interrupts = <15 1>;
33 /* It is an interrupt and GPIO controller itself */
34 interrupt-controller;
35 gpio-controller;
36 intel,muxctl = <0>;
37 };
38
39 testuser@20 {
40 compatible = "example,testuser";
41 /* User the 11th GPIO line as an active high triggered
42 * level interrupt
43 */
44 interrupts = <11 8>;
45 interrupt-parent = <&pcigpio>;
46 /* Use this GPIO also with the gpio functions */
47 gpios = <&pcigpio 11 0>;
48 };