diff options
author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2014-12-17 11:18:49 -0500 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-01-08 10:14:30 -0500 |
commit | 596bdcf7782899d699c13aad7b20f1d99810d1fa (patch) | |
tree | 61f965a1ef5034d19496b439199fd08dc00cb26f /Documentation/devicetree | |
parent | caa9657085bd1fcc8e5ba8f21799c75a4d8a70b5 (diff) |
clk: shmobile: r8a73a4 common clock framework implementation
Driver for the R8A73A4's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt new file mode 100644 index 000000000000..ece92393e80d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt | |||
@@ -0,0 +1,33 @@ | |||
1 | * Renesas R8A73A4 Clock Pulse Generator (CPG) | ||
2 | |||
3 | The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs | ||
4 | and several fixed ratio dividers. | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible: Must be "renesas,r8a73a4-cpg-clocks" | ||
9 | |||
10 | - reg: Base address and length of the memory resource used by the CPG | ||
11 | |||
12 | - clocks: Reference to the parent clocks ("extal1" and "extal2") | ||
13 | |||
14 | - #clock-cells: Must be 1 | ||
15 | |||
16 | - clock-output-names: The names of the clocks. Supported clocks are "main", | ||
17 | "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", | ||
18 | "m1", "m2", "zx", "zs", and "hp". | ||
19 | |||
20 | |||
21 | Example | ||
22 | ------- | ||
23 | |||
24 | cpg_clocks: cpg_clocks@e6150000 { | ||
25 | compatible = "renesas,r8a73a4-cpg-clocks"; | ||
26 | reg = <0 0xe6150000 0 0x10000>; | ||
27 | clocks = <&extal1_clk>, <&extal2_clk>; | ||
28 | #clock-cells = <1>; | ||
29 | clock-output-names = "main", "pll0", "pll1", "pll2", | ||
30 | "pll2s", "pll2h", "z", "z2", | ||
31 | "i", "m3", "b", "m1", "m2", | ||
32 | "zx", "zs", "hp"; | ||
33 | }; | ||