diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-21 15:30:30 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-21 15:30:30 -0500 |
commit | 18a8d49973667aa016e68826eeb374788b7c63b0 (patch) | |
tree | d7f90fcf05087ce50ee931b596e60e4c3c082a29 /Documentation/devicetree | |
parent | c189cb8ef62832f33b6cf757350a0270532a1ad8 (diff) | |
parent | ec02ace8ca0a50eef430d3676de5c5fa978b0e29 (diff) |
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
Diffstat (limited to 'Documentation/devicetree')
11 files changed, 202 insertions, 21 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt index 6d3d5f80c1c3..6bf1e7493f61 100644 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt | |||
@@ -34,6 +34,8 @@ Required Properties for Clock Controller: | |||
34 | - "samsung,exynos7-clock-peris" | 34 | - "samsung,exynos7-clock-peris" |
35 | - "samsung,exynos7-clock-fsys0" | 35 | - "samsung,exynos7-clock-fsys0" |
36 | - "samsung,exynos7-clock-fsys1" | 36 | - "samsung,exynos7-clock-fsys1" |
37 | - "samsung,exynos7-clock-mscl" | ||
38 | - "samsung,exynos7-clock-aud" | ||
37 | 39 | ||
38 | - reg: physical base address of the controller and the length of | 40 | - reg: physical base address of the controller and the length of |
39 | memory mapped region. | 41 | memory mapped region. |
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller: | |||
53 | - dout_sclk_bus1_pll | 55 | - dout_sclk_bus1_pll |
54 | - dout_sclk_cc_pll | 56 | - dout_sclk_cc_pll |
55 | - dout_sclk_mfc_pll | 57 | - dout_sclk_mfc_pll |
58 | - dout_sclk_aud_pll | ||
56 | 59 | ||
57 | Input clocks for top1 clock controller: | 60 | Input clocks for top1 clock controller: |
58 | - fin_pll | 61 | - fin_pll |
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller: | |||
76 | - sclk_uart1 | 79 | - sclk_uart1 |
77 | - sclk_uart2 | 80 | - sclk_uart2 |
78 | - sclk_uart3 | 81 | - sclk_uart3 |
82 | - sclk_spi0 | ||
83 | - sclk_spi1 | ||
84 | - sclk_spi2 | ||
85 | - sclk_spi3 | ||
86 | - sclk_spi4 | ||
87 | - sclk_i2s1 | ||
88 | - sclk_pcm1 | ||
89 | - sclk_spdif | ||
79 | 90 | ||
80 | Input clocks for peris clock controller: | 91 | Input clocks for peris clock controller: |
81 | - fin_pll | 92 | - fin_pll |
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller: | |||
91 | - dout_aclk_fsys1_200 | 102 | - dout_aclk_fsys1_200 |
92 | - dout_sclk_mmc0 | 103 | - dout_sclk_mmc0 |
93 | - dout_sclk_mmc1 | 104 | - dout_sclk_mmc1 |
105 | |||
106 | Input clocks for aud clock controller: | ||
107 | - fin_pll | ||
108 | - fout_aud_pll | ||
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt index ded5d6212c84..c6620bc96703 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt | |||
@@ -1,4 +1,4 @@ | |||
1 | NVIDIA Tegra124 Clock And Reset Controller | 1 | NVIDIA Tegra124 and Tegra132 Clock And Reset Controller |
2 | 2 | ||
3 | This binding uses the common clock binding: | 3 | This binding uses the common clock binding: |
4 | Documentation/devicetree/bindings/clock/clock-bindings.txt | 4 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible | |||
7 | for muxing and gating Tegra's clocks, and setting their rates. | 7 | for muxing and gating Tegra's clocks, and setting their rates. |
8 | 8 | ||
9 | Required properties : | 9 | Required properties : |
10 | - compatible : Should be "nvidia,tegra124-car" | 10 | - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" |
11 | - reg : Should contain CAR registers location and length | 11 | - reg : Should contain CAR registers location and length |
12 | - clocks : Should contain phandle and clock specifiers for two clocks: | 12 | - clocks : Should contain phandle and clock specifiers for two clocks: |
13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". | 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". |
14 | - #clock-cells : Should be 1. | 14 | - #clock-cells : Should be 1. |
15 | In clock consumers, this cell represents the clock ID exposed by the | 15 | In clock consumers, this cell represents the clock ID exposed by the |
16 | CAR. The assignments may be found in header file | 16 | CAR. The assignments may be found in the header files |
17 | <dt-bindings/clock/tegra124-car.h>. | 17 | <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common |
18 | to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h> | ||
19 | (for Tegra124-specific clocks). | ||
18 | - #reset-cells : Should be 1. | 20 | - #reset-cells : Should be 1. |
19 | In clock consumers, this cell represents the bit number in the CAR's | 21 | In clock consumers, this cell represents the bit number in the CAR's |
20 | array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. | 22 | array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. |
diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt new file mode 100644 index 000000000000..dd755be63a01 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | Qualcomm LPASS Clock & Reset Controller Binding | ||
2 | ------------------------------------------------ | ||
3 | |||
4 | Required properties : | ||
5 | - compatible : shall contain only one of the following: | ||
6 | |||
7 | "qcom,lcc-msm8960" | ||
8 | "qcom,lcc-apq8064" | ||
9 | "qcom,lcc-ipq8064" | ||
10 | |||
11 | - reg : shall contain base register location and length | ||
12 | - #clock-cells : shall contain 1 | ||
13 | - #reset-cells : shall contain 1 | ||
14 | |||
15 | Example: | ||
16 | clock-controller@28000000 { | ||
17 | compatible = "qcom,lcc-ipq8064"; | ||
18 | reg = <0x28000000 0x1000>; | ||
19 | #clock-cells = <1>; | ||
20 | #reset-cells = <1>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 266ff9d23229..df4a259a6898 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt | |||
@@ -1,6 +1,6 @@ | |||
1 | * Clock Block on Freescale CoreNet Platforms | 1 | * Clock Block on Freescale QorIQ Platforms |
2 | 2 | ||
3 | Freescale CoreNet chips take primary clocking input from the external | 3 | Freescale qoriq chips take primary clocking input from the external |
4 | SYSCLK signal. The SYSCLK input (frequency) is multiplied using | 4 | SYSCLK signal. The SYSCLK input (frequency) is multiplied using |
5 | multiple phase locked loops (PLL) to create a variety of frequencies | 5 | multiple phase locked loops (PLL) to create a variety of frequencies |
6 | which can then be passed to a variety of internal logic, including | 6 | which can then be passed to a variety of internal logic, including |
@@ -29,6 +29,7 @@ Required properties: | |||
29 | * "fsl,t4240-clockgen" | 29 | * "fsl,t4240-clockgen" |
30 | * "fsl,b4420-clockgen" | 30 | * "fsl,b4420-clockgen" |
31 | * "fsl,b4860-clockgen" | 31 | * "fsl,b4860-clockgen" |
32 | * "fsl,ls1021a-clockgen" | ||
32 | Chassis clock strings include: | 33 | Chassis clock strings include: |
33 | * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks | 34 | * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks |
34 | * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks | 35 | * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks |
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 2e18676bd4b5..0a80fa70ca26 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | |||
@@ -11,6 +11,7 @@ Required Properties: | |||
11 | 11 | ||
12 | - compatible: Must be one of the following | 12 | - compatible: Must be one of the following |
13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks | 13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks |
14 | - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks | ||
14 | - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks | 15 | - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks |
15 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks | 16 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks |
16 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks | 17 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks |
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt new file mode 100644 index 000000000000..ece92393e80d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt | |||
@@ -0,0 +1,33 @@ | |||
1 | * Renesas R8A73A4 Clock Pulse Generator (CPG) | ||
2 | |||
3 | The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs | ||
4 | and several fixed ratio dividers. | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible: Must be "renesas,r8a73a4-cpg-clocks" | ||
9 | |||
10 | - reg: Base address and length of the memory resource used by the CPG | ||
11 | |||
12 | - clocks: Reference to the parent clocks ("extal1" and "extal2") | ||
13 | |||
14 | - #clock-cells: Must be 1 | ||
15 | |||
16 | - clock-output-names: The names of the clocks. Supported clocks are "main", | ||
17 | "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", | ||
18 | "m1", "m2", "zx", "zs", and "hp". | ||
19 | |||
20 | |||
21 | Example | ||
22 | ------- | ||
23 | |||
24 | cpg_clocks: cpg_clocks@e6150000 { | ||
25 | compatible = "renesas,r8a73a4-cpg-clocks"; | ||
26 | reg = <0 0xe6150000 0 0x10000>; | ||
27 | clocks = <&extal1_clk>, <&extal2_clk>; | ||
28 | #clock-cells = <1>; | ||
29 | clock-output-names = "main", "pll0", "pll1", "pll2", | ||
30 | "pll2s", "pll2h", "z", "z2", | ||
31 | "i", "m3", "b", "m1", "m2", | ||
32 | "zx", "zs", "hp"; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index e6ad35b894f9..b02944fba9de 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | |||
@@ -8,15 +8,18 @@ Required Properties: | |||
8 | - compatible: Must be one of | 8 | - compatible: Must be one of |
9 | - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG | 9 | - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG |
10 | - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG | 10 | - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG |
11 | - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG | ||
11 | - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG | 12 | - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG |
12 | - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG | 13 | - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG |
13 | 14 | ||
14 | - reg: Base address and length of the memory resource used by the CPG | 15 | - reg: Base address and length of the memory resource used by the CPG |
15 | 16 | ||
16 | - clocks: Reference to the parent clock | 17 | - clocks: References to the parent clocks: first to the EXTAL clock, second |
18 | to the USB_EXTAL clock | ||
17 | - #clock-cells: Must be 1 | 19 | - #clock-cells: Must be 1 |
18 | - clock-output-names: The names of the clocks. Supported clocks are "main", | 20 | - clock-output-names: The names of the clocks. Supported clocks are "main", |
19 | "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z" | 21 | "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and |
22 | "adsp" | ||
20 | 23 | ||
21 | 24 | ||
22 | Example | 25 | Example |
@@ -26,8 +29,9 @@ Example | |||
26 | compatible = "renesas,r8a7790-cpg-clocks", | 29 | compatible = "renesas,r8a7790-cpg-clocks", |
27 | "renesas,rcar-gen2-cpg-clocks"; | 30 | "renesas,rcar-gen2-cpg-clocks"; |
28 | reg = <0 0xe6150000 0 0x1000>; | 31 | reg = <0 0xe6150000 0 0x1000>; |
29 | clocks = <&extal_clk>; | 32 | clocks = <&extal_clk &usb_extal_clk>; |
30 | #clock-cells = <1>; | 33 | #clock-cells = <1>; |
31 | clock-output-names = "main", "pll0, "pll1", "pll3", | 34 | clock-output-names = "main", "pll0, "pll1", "pll3", |
32 | "lb", "qspi", "sdh", "sd0", "sd1", "z"; | 35 | "lb", "qspi", "sdh", "sd0", "sd1", "z", |
36 | "rcan", "adsp"; | ||
33 | }; | 37 | }; |
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 67b2b99f2b33..60b44285250d 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt | |||
@@ -26,7 +26,7 @@ Required properties: | |||
26 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s | 26 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
27 | "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 | 27 | "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 |
28 | "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 | 28 | "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 |
29 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 | 29 | "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 |
30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 | 30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 | 31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
32 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 | 32 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 |
@@ -55,9 +55,11 @@ Required properties: | |||
55 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 | 55 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
56 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 | 56 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |
57 | "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 | 57 | "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 |
58 | "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 | 58 | "allwinner,sun4i-a10-mmc-clk" - for the MMC clock |
59 | "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 | 59 | "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 |
60 | "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 | ||
60 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks | 61 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks |
62 | "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 | ||
61 | "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 | 63 | "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 |
62 | "allwinner,sun7i-a20-out-clk" - for the external output clocks | 64 | "allwinner,sun7i-a20-out-clk" - for the external output clocks |
63 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 | 65 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 |
@@ -73,7 +75,9 @@ Required properties for all clocks: | |||
73 | - #clock-cells : from common clock binding; shall be set to 0 except for | 75 | - #clock-cells : from common clock binding; shall be set to 0 except for |
74 | the following compatibles where it shall be set to 1: | 76 | the following compatibles where it shall be set to 1: |
75 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", | 77 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", |
76 | "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk" | 78 | "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", |
79 | "allwinner,*-usb-clk", "allwinner,*-mmc-clk", | ||
80 | "allwinner,*-mmc-config-clk" | ||
77 | - clock-output-names : shall be the corresponding names of the outputs. | 81 | - clock-output-names : shall be the corresponding names of the outputs. |
78 | If the clock module only has one output, the name shall be the | 82 | If the clock module only has one output, the name shall be the |
79 | module name. | 83 | module name. |
@@ -81,6 +85,10 @@ Required properties for all clocks: | |||
81 | And "allwinner,*-usb-clk" clocks also require: | 85 | And "allwinner,*-usb-clk" clocks also require: |
82 | - reset-cells : shall be set to 1 | 86 | - reset-cells : shall be set to 1 |
83 | 87 | ||
88 | The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: | ||
89 | - #reset-cells : shall be set to 1 | ||
90 | - resets : shall be the reset control phandle for the mmc block. | ||
91 | |||
84 | For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate | 92 | For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate |
85 | dummy clocks at 25 MHz and 125 MHz, respectively. See example. | 93 | dummy clocks at 25 MHz and 125 MHz, respectively. See example. |
86 | 94 | ||
@@ -95,6 +103,14 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output | |||
95 | is the normal PLL6 output, or "pll6". The second output is rate doubled | 103 | is the normal PLL6 output, or "pll6". The second output is rate doubled |
96 | PLL6, or "pll6x2". | 104 | PLL6, or "pll6x2". |
97 | 105 | ||
106 | The "allwinner,*-mmc-clk" clocks have three different outputs: the | ||
107 | main clock, with the ID 0, and the output and sample clocks, with the | ||
108 | IDs 1 and 2, respectively. | ||
109 | |||
110 | The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output | ||
111 | per mmc controller. The number of outputs is determined by the size of | ||
112 | the address block, which is related to the overall mmc block. | ||
113 | |||
98 | For example: | 114 | For example: |
99 | 115 | ||
100 | osc24M: clk@01c20050 { | 116 | osc24M: clk@01c20050 { |
@@ -138,11 +154,11 @@ cpu: cpu@01c20054 { | |||
138 | }; | 154 | }; |
139 | 155 | ||
140 | mmc0_clk: clk@01c20088 { | 156 | mmc0_clk: clk@01c20088 { |
141 | #clock-cells = <0>; | 157 | #clock-cells = <1>; |
142 | compatible = "allwinner,sun4i-mod0-clk"; | 158 | compatible = "allwinner,sun4i-a10-mmc-clk"; |
143 | reg = <0x01c20088 0x4>; | 159 | reg = <0x01c20088 0x4>; |
144 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | 160 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
145 | clock-output-names = "mmc0"; | 161 | clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; |
146 | }; | 162 | }; |
147 | 163 | ||
148 | mii_phy_tx_clk: clk@2 { | 164 | mii_phy_tx_clk: clk@2 { |
@@ -170,3 +186,16 @@ gmac_clk: clk@01c20164 { | |||
170 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | 186 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; |
171 | clock-output-names = "gmac"; | 187 | clock-output-names = "gmac"; |
172 | }; | 188 | }; |
189 | |||
190 | mmc_config_clk: clk@01c13000 { | ||
191 | compatible = "allwinner,sun9i-a80-mmc-config-clk"; | ||
192 | reg = <0x01c13000 0x10>; | ||
193 | clocks = <&ahb0_gates 8>; | ||
194 | clock-names = "ahb"; | ||
195 | resets = <&ahb0_resets 8>; | ||
196 | reset-names = "ahb"; | ||
197 | #clock-cells = <1>; | ||
198 | #reset-cells = <1>; | ||
199 | clock-output-names = "mmc0_config", "mmc1_config", | ||
200 | "mmc2_config", "mmc3_config"; | ||
201 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt new file mode 100644 index 000000000000..616836e7e1e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,cdce706.txt | |||
@@ -0,0 +1,42 @@ | |||
1 | Bindings for Texas Instruments CDCE706 programmable 3-PLL clock | ||
2 | synthesizer/multiplier/divider. | ||
3 | |||
4 | Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf | ||
5 | |||
6 | I2C device node required properties: | ||
7 | - compatible: shall be "ti,cdce706". | ||
8 | - reg: i2c device address, shall be in range [0x68...0x6b]. | ||
9 | - #clock-cells: from common clock binding; shall be set to 1. | ||
10 | - clocks: from common clock binding; list of parent clock | ||
11 | handles, shall be reference clock(s) connected to CLK_IN0 | ||
12 | and CLK_IN1 pins. | ||
13 | - clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0 | ||
14 | in case of crystal oscillator or differential signal input | ||
15 | configuration. Use clk_in0 and clk_in1 in case of independent | ||
16 | single-ended LVCMOS inputs configuration. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | clocks { | ||
21 | clk54: clk54 { | ||
22 | #clock-cells = <0>; | ||
23 | compatible = "fixed-clock"; | ||
24 | clock-frequency = <54000000>; | ||
25 | }; | ||
26 | }; | ||
27 | ... | ||
28 | i2c0: i2c-master@0d090000 { | ||
29 | ... | ||
30 | cdce706: clock-synth@69 { | ||
31 | compatible = "ti,cdce706"; | ||
32 | #clock-cells = <1>; | ||
33 | reg = <0x69>; | ||
34 | clocks = <&clk54>; | ||
35 | clock-names = "clk_in0"; | ||
36 | }; | ||
37 | }; | ||
38 | ... | ||
39 | simple-audio-card,codec { | ||
40 | ... | ||
41 | clocks = <&cdce706 4>; | ||
42 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documentation/devicetree/bindings/clock/ti/fapll.txt new file mode 100644 index 000000000000..c19b3f253b8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/fapll.txt | |||
@@ -0,0 +1,33 @@ | |||
1 | Binding for Texas Instruments FAPLL clock. | ||
2 | |||
3 | Binding status: Unstable - ABI compatibility may be broken in the future | ||
4 | |||
5 | This binding uses the common clock binding[1]. It assumes a | ||
6 | register-mapped FAPLL with usually two selectable input clocks | ||
7 | (reference clock and bypass clock), and one or more child | ||
8 | syntesizers. | ||
9 | |||
10 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
11 | |||
12 | Required properties: | ||
13 | - compatible : shall be "ti,dm816-fapll-clock" | ||
14 | - #clock-cells : from common clock binding; shall be set to 0. | ||
15 | - clocks : link phandles of parent clocks (clk-ref and clk-bypass) | ||
16 | - reg : address and length of the register set for controlling the FAPLL. | ||
17 | |||
18 | Examples: | ||
19 | main_fapll: main_fapll { | ||
20 | #clock-cells = <1>; | ||
21 | compatible = "ti,dm816-fapll-clock"; | ||
22 | reg = <0x400 0x40>; | ||
23 | clocks = <&sys_clkin_ck &sys_clkin_ck>; | ||
24 | clock-indices = <1>, <2>, <3>, <4>, <5>, | ||
25 | <6>, <7>; | ||
26 | clock-output-names = "main_pll_clk1", | ||
27 | "main_pll_clk2", | ||
28 | "main_pll_clk3", | ||
29 | "main_pll_clk4", | ||
30 | "main_pll_clk5", | ||
31 | "main_pll_clk6", | ||
32 | "main_pll_clk7"; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 91b3a3467150..4bf41d833804 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | |||
@@ -10,8 +10,8 @@ Absolute maximum transfer rate is 200MB/s | |||
10 | Required properties: | 10 | Required properties: |
11 | - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc" | 11 | - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc" |
12 | - reg : mmc controller base registers | 12 | - reg : mmc controller base registers |
13 | - clocks : a list with 2 phandle + clock specifier pairs | 13 | - clocks : a list with 4 phandle + clock specifier pairs |
14 | - clock-names : must contain "ahb" and "mmc" | 14 | - clock-names : must contain "ahb", "mmc", "output" and "sample" |
15 | - interrupts : mmc controller interrupt | 15 | - interrupts : mmc controller interrupt |
16 | 16 | ||
17 | Optional properties: | 17 | Optional properties: |
@@ -25,8 +25,8 @@ Examples: | |||
25 | mmc0: mmc@01c0f000 { | 25 | mmc0: mmc@01c0f000 { |
26 | compatible = "allwinner,sun5i-a13-mmc"; | 26 | compatible = "allwinner,sun5i-a13-mmc"; |
27 | reg = <0x01c0f000 0x1000>; | 27 | reg = <0x01c0f000 0x1000>; |
28 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | 28 | clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>; |
29 | clock-names = "ahb", "mod"; | 29 | clock-names = "ahb", "mod", "output", "sample"; |
30 | interrupts = <0 32 4>; | 30 | interrupts = <0 32 4>; |
31 | status = "disabled"; | 31 | status = "disabled"; |
32 | }; | 32 | }; |