Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As always, this tends to be one of our bigger branches.  There are
  lots of updates this release, but not that many jumps out as something
  that needs more detailed coverage.  Some of the highlights are:

   - DTs for the new Annapurna Labs Alpine platform

   - more graphics DT pieces falling into place on Exynos, bridges,
     clocks.

   - plenty of DT updates for Qualcomm platforms for various IP blocks

   - some churn on Tegra due to switch-over to tool-generated pinctrl
     data

   - misc fixes and updates for Atmel at91 platforms

   - various DT updates to add IP block support on Broadcom's Cygnus
     platforms

   - more updates for Renesas platforms as DT support is added for
     various IP blocks (IPMMU, display, audio, etc)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (231 commits)
  ARM: dts: alpine: add internal pci
  Revert "ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135."
  ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB
  ARM: dts: qcom: Add idle state device nodes for 8064
  ARM: dts: qcom: Add idle states device nodes for 8084
  ARM: dts: qcom: Add idle states device nodes for 8974/8074
  ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs
  ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
  ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
  devicetree: bindings: Document qcom,idle-states
  devicetree: bindings: Update qcom,saw2 node bindings
  dt-bindings: Add #defines for MSM8916 clocks and resets
  arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree
  arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes
  arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
  arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
  arm: dts: qcom: Add LCC nodes
  arm: dts: qcom: Add TCSR support for MSM8960
  arm: dts: qcom: Add TCSR support for MSM8660
  arm: dts: qcom: Add TCSR support for IPQ8064
  ...

15 files changed, 388 insertions, 12 deletions

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 1e097037349c..5da38c5ed476 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,9 @@ Optional Properties:
         - pclkN, clkN: Pairs of parent of input clock and input clock to the
                 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
                 are supported currently.
+        - asbN: Clocks required by asynchronous bridges (ASB) present in
+                the power domain. These clock should be enabled during power
+                domain on/off operations.
 - power-domains: phandle pointing to the parent power domain, for more details
                  see Documentation/devicetree/bindings/power/power_domain.txt
 
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 1e0d21201d3a..2da059a4790c 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -18,6 +18,8 @@ Main node required properties:
         "arm,arm11mp-gic"
         "brcm,brahma-b15-gic"
         "arm,arm1176jzf-devchip-gic"
+        "qcom,msm-8660-qgic"
+        "qcom,msm-qgic2"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
index 925ecbf6e7b7..4f40ff3fee4b 100644
--- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
@@ -42,6 +42,7 @@ board. Currently known boards are:
 "lacie,cloudbox"
 "lacie,inetspace_v2"
 "lacie,laplug"
+"lacie,nas2big"
 "lacie,netspace_lite_v2"
 "lacie,netspace_max_v2"
 "lacie,netspace_mini_v2"
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
new file mode 100644
index 000000000000..06df04cc827a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
@@ -0,0 +1,84 @@
+QCOM Idle States for cpuidle driver
+
+ARM provides idle-state node to define the cpuidle states, as defined in [1].
+cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
+states. Idle states have different enter/exit latency and residency values.
+The idle states supported by the QCOM SoC are defined as -
+
+    * Standby
+    * Retention
+    * Standalone Power Collapse (Standalone PC or SPC)
+    * Power Collapse (PC)
+
+Standby: Standby does a little more in addition to architectural clock gating.
+When the WFI instruction is executed the ARM core would gate its internal
+clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+trigger to execute the SPM state machine. The SPM state machine waits for the
+interrupt to trigger the core back in to active. This triggers the cache
+hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+the SPM state machine out of its wait, the next step is to ensure that the
+cache hierarchy is also out of standby, and then the cpu is allowed to resume
+execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
+driver and is not defined in the DT. The SPM state machine should be
+configured to execute this state by default and after executing every other
+state below.
+
+Retention: Retention is a low power state where the core is clock gated and
+the memory and the registers associated with the core are retained. The
+voltage may be reduced to the minimum value needed to keep the processor
+registers active. The SPM should be configured to execute the retention
+sequence and would wait for interrupt, before restoring the cpu to execution
+state. Retention may have a slightly higher latency than Standby.
+
+Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+between the time it enters idle and the next known wake up. SPC mode is used
+to indicate a core entering a power down state without consulting any other
+cpu or the system resources. This helps save power only on that core.  The SPM
+sequence for this idle state is programmed to power down the supply to the
+core, wait for the interrupt, restore power to the core, and ensure the
+system state including cache hierarchy is ready before allowing core to
+resume. Applying power and resetting the core causes the core to warmboot
+back into Elevation Level (EL) which trampolines the control back to the
+kernel. Entering a power down state for the cpu, needs to be done by trapping
+into a EL. Failing to do so, would result in a crash enforced by the warm boot
+code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+be flushed in s/w, before powering down the core.
+
+Power Collapse: This state is similar to the SPC mode, but distinguishes
+itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+modes. In a hierarchical power domain SoC, this means L2 and other caches can
+be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+voltages reduced, provided all cpus enter this state.  Since the span of low
+power modes possible at this state is vast, the exit latency and the residency
+of this low power mode would be considered high even though at a cpu level,
+this essentially is cpu power down. The SPM in this state also may handshake
+with the Resource power manager (RPM) processor in the SoC to indicate a
+complete application processor subsystem shut down.
+
+The idle-state for QCOM SoCs are distinguished by the compatible property of
+the idle-states device node.
+
+The devicetree representation of the idle state should be -
+
+Required properties:
+
+- compatible: Must be one of -
+                        "qcom,idle-state-ret",
+                        "qcom,idle-state-spc",
+                        "qcom,idle-state-pc",
+                and "arm,idle-state".
+
+Other required and optional properties are specified in [1].
+
+Example:
+
+        idle-states {
+                CPU_SPC: spc {
+                        compatible = "qcom,idle-state-spc", "arm,idle-state";
+                        entry-latency-us = <150>;
+                        exit-latency-us = <200>;
+                        min-residency-us = <2000>;
+                };
+        };
+
+[1]. Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index 1505fb8e131a..ae4afc6dcfe0 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -2,22 +2,31 @@ SPM AVS Wrapper 2 (SAW2)
 
 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
 Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-micro-controller that transitions a piece of hardware (like a processor or
+power-controller that transitions a piece of hardware (like a processor or
 subsystem) into and out of low power modes via a direct connection to
 the PMIC. It can also be wired up to interact with other processors in the
 system, notifying them when a low power state is entered or exited.
 
+Multiple revisions of the SAW hardware are supported using these Device Nodes.
+SAW2 revisions differ in the register offset and configuration data. Also, the
+same revision of the SAW in different SoCs may have different configuration
+data due the the differences in hardware capabilities. Hence the SoC name, the
+version of the SAW hardware in that SoC and the distinction between cpu (big
+or Little) or cache, may be needed to uniquely identify the SAW register
+configuration and initialization data. The compatible string is used to
+indicate this parameter.
+
 PROPERTIES
 
 - compatible:
         Usage: required
         Value type: <string>
-        Definition: shall contain "qcom,saw2". A more specific value should be
-                    one of:
-                         "qcom,saw2-v1"
-                         "qcom,saw2-v1.1"
-                         "qcom,saw2-v2"
-                         "qcom,saw2-v2.1"
+        Definition: Must have
+                        "qcom,saw2"
+                    A more specific value could be one of:
+                        "qcom,apq8064-saw2-v1.1-cpu"
+                        "qcom,msm8974-saw2-v2.1-cpu"
+                        "qcom,apq8084-saw2-v2.1-cpu"
 
 - reg:
         Usage: required
@@ -26,10 +35,23 @@ PROPERTIES
                     the register region. An optional second element specifies
                     the base address and size of the alias register region.
 
+- regulator:
+        Usage: optional
+        Value type: boolean
+        Definition: Indicates that this SPM device acts as a regulator device
+                        device for the core (CPU or Cache) the SPM is attached
+                        to.
 
-Example:
+Example 1:
 
-        regulator@2099000 {
+        power-controller@2099000 {
                 compatible = "qcom,saw2";
                 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                regulator;
+        };
+
+Example 2:
+        saw0: power-controller@f9089000 {
+                compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
         };
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 6809e4e51ed2..60d4a1e0a9b5 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -22,3 +22,7 @@ Rockchip platforms device tree bindings
       - compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
     or
       - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
+
+- ChipSPARK PopMetal-RK3288 board:
+    Required root node properties:
+      - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
new file mode 100644
index 000000000000..ea670a5d7ee3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
@@ -0,0 +1,32 @@
+NVIDIA Tegra Activity Monitor
+
+The activity monitor block collects statistics about the behaviour of other
+components in the system. This information can be used to derive the rate at
+which the external memory needs to be clocked in order to serve all requests
+from the monitored clients.
+
+Required properties:
+- compatible: should be "nvidia,tegra<chip>-actmon"
+- reg: offset and length of the register set for the device
+- interrupts: standard interrupt property
+- clocks: Must contain a phandle and clock specifier pair for each entry in
+clock-names. See ../../clock/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - actmon
+  - emc
+- resets: Must contain an entry for each entry in reset-names. See
+../../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - actmon
+
+Example:
+        actmon@6000c800 {
+                compatible = "nvidia,tegra124-actmon";
+                reg = <0x0 0x6000c800 0x0 0x400>;
+                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
+                         <&tegra_car TEGRA124_CLK_EMC>;
+                clock-names = "actmon", "emc";
+                resets = <&tegra_car 119>;
+                reset-names = "actmon";
+        };
diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt
new file mode 100644
index 000000000000..ac23de855641
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti,omap3isp.txt
@@ -0,0 +1,71 @@
+OMAP 3 ISP Device Tree bindings
+===============================
+
+The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
+
+Required properties
+===================
+
+compatible      : must contain "ti,omap3-isp"
+
+reg             : the two registers sets (physical address and length) for the
+                  ISP. The first set contains the core ISP registers up to
+                  the end of the SBL block. The second set contains the
+                  CSI PHYs and receivers registers.
+interrupts      : the ISP interrupt specifier
+iommus          : phandle and IOMMU specifier for the IOMMU that serves the ISP
+syscon          : the phandle and register offset to the Complex I/O or CSI-PHY
+                  register
+ti,phy-type     : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
+                  1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
+#clock-cells    : Must be 1 --- the ISP provides two external clocks,
+                  cam_xclka and cam_xclkb, at indices 0 and 1,
+                  respectively. Please find more information on common
+                  clock bindings in ../clock/clock-bindings.txt.
+
+Port nodes (optional)
+---------------------
+
+More documentation on these bindings is available in
+video-interfaces.txt in the same directory.
+
+reg             : The interface:
+                  0 - parallel (CCDC)
+                  1 - CSIPHY1 -- CSI2C / CCP2B on 3630;
+                      CSI1 -- CSIb on 3430
+                  2 - CSIPHY2 -- CSI2A / CCP2B on 3630;
+                      CSI2 -- CSIa on 3430
+
+Optional properties
+===================
+
+vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
+vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
+
+Endpoint nodes
+--------------
+
+lane-polarities : lane polarity (required on CSI-2)
+                  0 -- not inverted; 1 -- inverted
+data-lanes      : an array of data lanes from 1 to 3. The length can
+                  be either 1 or 2. (required on CSI-2)
+clock-lanes     : the clock lane (from 1 to 3). (required on CSI-2)
+
+
+Example
+=======
+
+                isp@480bc000 {
+                        compatible = "ti,omap3-isp";
+                        reg = <0x480bc000 0x12fc
+                               0x480bd800 0x0600>;
+                        interrupts = <24>;
+                        iommus = <&mmu_isp>;
+                        syscon = <&scm_conf 0x2f0>;
+                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                        #clock-cells = <1>;
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 000000000000..e90519d566a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals.  This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible:   Should contain:
+                "qcom,tcsr-ipq8064", "syscon" for IPQ8064
+                "qcom,tcsr-apq8064", "syscon" for APQ8064
+                "qcom,tcsr-msm8660", "syscon" for MSM8660
+                "qcom,tcsr-msm8960", "syscon" for MSM8960
+                "qcom,tcsr-msm8974", "syscon" for MSM8974
+                "qcom,tcsr-apq8084", "syscon" for APQ8084
+                "qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+        tcsr: syscon@1a400000 {
+                compatible = "qcom,tcsr-msm8960", "syscon";
+                reg = <0x1a400000 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
new file mode 100644
index 000000000000..2a3d90de18ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
@@ -0,0 +1,47 @@
+TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices
+
+This node provides properties for controlling the wilink wireless device. The
+node is expected to be specified as a child node to the SDIO controller that
+connects the device to the system.
+
+Required properties:
+ - compatible: should be one of the following:
+    * "ti,wl1271"
+    * "ti,wl1273"
+    * "ti,wl1281"
+    * "ti,wl1283"
+    * "ti,wl1801"
+    * "ti,wl1805"
+    * "ti,wl1807"
+    * "ti,wl1831"
+    * "ti,wl1835"
+    * "ti,wl1837"
+ - interrupts : specifies attributes for the out-of-band interrupt.
+
+Optional properties:
+ - interrupt-parent : the phandle for the interrupt controller to which the
+        device interrupts are connected.
+ - ref-clock-frequency : ref clock frequency in Hz
+ - tcxo-clock-frequency : tcxo clock frequency in Hz
+
+Note: the *-clock-frequency properties assume internal clocks. In case of external
+clock, new bindings (for parsing the clock nodes) have to be added.
+
+Example:
+
+&mmc3 {
+        status = "okay";
+        vmmc-supply = <&wlan_en_reg>;
+        bus-width = <4>;
+        cap-power-off-card;
+        keep-power-in-suspend;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1835";
+                reg = <2>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
index 342eedd10050..54c2a155c783 100644
--- a/Documentation/devicetree/bindings/serial/omap_serial.txt
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -4,7 +4,27 @@ Required properties:
 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- reg : address and length of the register space
+- interrupts or interrupts-extended : Should contain the uart interrupt
+                                      specifier or both the interrupt
+                                      controller phandle and interrupt
+                                      specifier.
 - ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
 
 Optional properties:
 - clock-frequency : frequency of the clock input to the UART
+- dmas : DMA specifier, consisting of a phandle to the DMA controller
+         node and a DMA channel number.
+- dma-names : "rx" for receive channel, "tx" for transmit channel.
+
+Example:
+
+                uart4: serial@49042000 {
+                        compatible = "ti,omap3-uart";
+                        reg = <0x49042000 0x400>;
+                        interrupts = <80>;
+                        dmas = <&sdma 81 &sdma 82>;
+                        dma-names = "tx", "rx";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
new file mode 100644
index 000000000000..ddeb5b6a53c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -0,0 +1,58 @@
+MediaTek PMIC Wrapper Driver
+
+This document describes the binding for the MediaTek PMIC wrapper.
+
+On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
+is not directly visible to the CPU, but only through the PMIC wrapper
+inside the SoC. The communication between the SoC and the PMIC can
+optionally be encrypted. Also a non standard Dual IO SPI mode can be
+used to increase speed.
+
+IP Pairing
+
+on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
+The signals of these pins are routed over the SPI bus using the pwrap
+bridge. In the binding description below the properties needed for bridging
+are marked with "IP Pairing". These are optional on SoCs which do not support
+IP Pairing
+
+Required properties in pwrap device node.
+- compatible:
+        "mediatek,mt8135-pwrap" for MT8135 SoCs
+        "mediatek,mt8173-pwrap" for MT8173 SoCs
+- interrupts: IRQ for pwrap in SOC
+- reg-names: Must include the following entries:
+  "pwrap": Main registers base
+  "pwrap-bridge": bridge base (IP Pairing)
+- reg: Must contain an entry for each entry in reg-names.
+- reset-names: Must include the following entries:
+  "pwrap"
+  "pwrap-bridge" (IP Pairing)
+- resets: Must contain an entry for each entry in reset-names.
+- clock-names: Must include the following entries:
+  "spi": SPI bus clock
+  "wrap": Main module clock
+- clocks: Must contain an entry for each entry in clock-names.
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+  See the following for child node definitions:
+  Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+        pwrap: pwrap@1000f000 {
+                compatible = "mediatek,mt8135-pwrap";
+                reg = <0 0x1000f000 0 0x1000>,
+                        <0 0x11017000 0 0x1000>;
+                reg-names = "pwrap", "pwrap-bridge";
+                interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
+                                <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+                reset-names = "pwrap", "pwrap-bridge";
+                clocks = <&clk26m>, <&clk26m>;
+                clock-names = "spi", "wrap";
+
+                pmic {
+                        compatible = "mediatek,mt6397";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
index 1ab6bc8404d5..f6a715e4ef43 100644
--- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt
+++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
@@ -4,9 +4,9 @@ Required properties:
 - compatible: "ti,omap-twl4030"
 - ti,model: Name of the sound card (for example "omap3beagle")
 - ti,mcbsp: phandle for the McBSP node
-- ti,codec: phandle for the twl4030 audio node
 
 Optional properties:
+- ti,codec: phandle for the twl4030 audio node
 - ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl
 - ti, jack-det-gpio: Jack detect GPIO
 - ti,audio-routing: List of connections between audio components.
@@ -59,5 +59,4 @@ sound {
         ti,model = "omap3beagle";
 
         ti,mcbsp = <&mcbsp2>;
-        ti,codec = <&twl_audio>;
 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 54c1d5790358..83737a3403d7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -84,6 +84,7 @@ globalscale	Globalscale Technologies, Inc.
 gmt     Global Mixed-mode Technology, Inc.
 goodix  Shenzhen Huiding Technology Co., Ltd.
 google  Google, Inc.
+grinn   Grinn
 gumstix Gumstix, Inc.
 gw      Gateworks Corporation
 hannstar        HannStar Display Corporation
diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
index f059dd0b3d28..ecb8da063d07 100644
--- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt
+++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
@@ -10,7 +10,9 @@ Required properties:
         "atmel,at91sam9g45es-lcdc" ,
         "atmel,at91sam9rl-lcdc" ,
         "atmel,at32ap-lcdc"
-- reg : Should contain 1 register ranges(address and length)
+- reg : Should contain 1 register ranges(address and length).
+        Can contain an additional register range(address and length)
+        for fixed framebuffer memory. Useful for dedicated memories.
 - interrupts : framebuffer controller interrupt
 - display: a phandle pointing to the display node
 
@@ -38,6 +40,14 @@ Example:
 
         };
 
+Example for fixed framebuffer memory:
+
+        fb0: fb@0x00500000 {
+                compatible = "atmel,at91sam9263-lcdc";
+                reg = <0x00700000 0x1000 0x70000000 0x200000>;
+                [...]
+        };
+
 Atmel LCDC Display
 -----------------------------------------------------
 Required properties (as per of_videomode_helper):