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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-07-23 17:34:10 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2013-08-26 04:58:11 -0400
commit6a721db180a22d8e2d59d864446309bc7a09c26f (patch)
tree9da6f6cccba5a87a701bcc87c9157a1717d7f0dc /Documentation/devicetree
parent70855bb5c608e4ac9dde5b669c3cf56914b713a2 (diff)
clk: sunxi: Add A31 clocks support
The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt6
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt83
2 files changed, 89 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index b24de1003947..c383d1259e5c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -8,6 +8,7 @@ Required properties:
8- compatible : shall be one of the following: 8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator 9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock 10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock 12 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sun4i-axi-clk" - for the AXI clock 13 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates 14 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
@@ -15,6 +16,8 @@ Required properties:
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 16 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
16 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 17 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
17 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s 18 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
19 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
20 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
18 "allwinner,sun4i-apb0-clk" - for the APB0 clock 21 "allwinner,sun4i-apb0-clk" - for the APB0 clock
19 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 22 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
20 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 23 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
@@ -24,6 +27,9 @@ Required properties:
24 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 27 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
25 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 28 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
26 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s 29 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
30 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
31 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
32 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
27 33
28Required properties for all clocks: 34Required properties for all clocks:
29- reg : shall be the control register address for the clock. 35- reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
new file mode 100644
index 000000000000..fe44932b5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
@@ -0,0 +1,83 @@
1Gate clock outputs
2------------------
3
4 * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk")
5
6 MIPI DSI 1
7
8 SS 5
9 DMA 6
10
11 MMC0 8
12 MMC1 9
13 MMC2 10
14 MMC3 11
15
16 NAND1 12
17 NAND0 13
18 SDRAM 14
19
20 GMAC 17
21 TS 18
22 HSTIMER 19
23 SPI0 20
24 SPI1 21
25 SPI2 22
26 SPI3 23
27 USB_OTG 24
28
29 EHCI0 26
30 EHCI1 27
31
32 OHCI0 29
33 OHCI1 30
34 OHCI2 31
35 VE 32
36
37 LCD0 36
38 LCD1 37
39
40 CSI 40
41
42 HDMI 43
43 DE_BE0 44
44 DE_BE1 45
45 DE_FE1 46
46 DE_FE1 47
47
48 MP 50
49
50 GPU 52
51
52 DEU0 55
53 DEU1 56
54 DRC0 57
55 DRC1 58
56
57 * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk")
58
59 CODEC 0
60
61 DIGITAL MIC 4
62 PIO 5
63
64 DAUDIO0 12
65 DAUDIO1 13
66
67 * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk")
68
69 I2C0 0
70 I2C1 1
71 I2C2 2
72 I2C3 3
73
74 UART0 16
75 UART1 17
76 UART2 18
77 UART3 19
78 UART4 20
79 UART5 21
80
81Notation:
82 [*]: The datasheet didn't mention these, but they are present on AW code
83 [**]: The datasheet had this marked as "NC" but they are used on AW code
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 03:34:06 -0500