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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-03-02 14:16:27 -0500
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-03-15 11:31:22 -0400
commitc8082d344ac4c05932fec1766e5e9ce72cf286ed (patch)
tree8a2a7a4b2a61b3780c669b916b33a0cde09a7722 /Documentation/devicetree
parent21ea52aadd6296480baad3b04fef87230517b54c (diff)
ARM: at91: add RSTC (Reset Controller) dt support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt12
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1aeaf6f2a1ba..a64f86717b5d 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -30,3 +30,15 @@ One interrupt per TC channel in a TC block:
30 reg = <0xfffdc000 0x100>; 30 reg = <0xfffdc000 0x100>;
31 interrupts = <26 4 27 4 28 4>; 31 interrupts = <26 4 27 4 28 4>;
32 }; 32 };
33
34RSTC Reset Controller required properties:
35- compatible: Should be "atmel,<chip>-rstc".
36 <chip> can be "at91sam9260" or "at91sam9g45"
37- reg: Should contain registers location and length
38
39Example:
40
41 rstc@fffffd00 {
42 compatible = "atmel,at91sam9260-rstc";
43 reg = <0xfffffd00 0x10>;
44 };