ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND

This patch adds basic DT bindings for OMAP GPMC.

The actual peripherals are instantiated from child nodes within the GPMC
node, and the only type of device that is currently supported is NAND.

Code was added to parse the generic GPMC timing parameters and some
documentation with examples on how to use them.

Successfully tested on an AM33xx board.

Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
[tony@atomide.com: updated to apply]
Signed-off-by: Tony Lindgren <tony@atomide.com>

2 files changed, 160 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
new file mode 100644
index 000000000000..5ddb2e9efaaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -0,0 +1,84 @@
+Device tree bindings for OMAP general purpose memory controllers (GPMC)
+
+The actual devices are instantiated from the child nodes of a GPMC node.
+
+Required properties:
+
+ - compatible:          Should be set to one of the following:
+
+                        ti,omap2420-gpmc (omap2420)
+                        ti,omap2430-gpmc (omap2430)
+                        ti,omap3430-gpmc (omap3430 & omap3630)
+                        ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
+                        ti,am3352-gpmc   (am335x devices)
+
+ - reg:                 A resource specifier for the register space
+                        (see the example below)
+ - ti,hwmods:           Should be set to "ti,gpmc" until the DT transition is
+                        completed.
+ - #address-cells:      Must be set to 2 to allow memory address translation
+ - #size-cells:         Must be set to 1 to allow CS address passing
+ - gpmc,num-cs:         The maximum number of chip-select lines that controller
+                        can support.
+ - gpmc,num-waitpins:   The maximum number of wait pins that controller can
+                        support.
+ - ranges:              Must be set up to reflect the memory layout with four
+                        integer values for each chip-select line in use:
+
+                           <cs-number> 0 <physical address of mapping> <size>
+
+                        Currently, calculated values derived from the contents
+                        of the per-CS register GPMC_CONFIG7 (as set up by the
+                        bootloader) are used for the physical address decoding.
+                        As this will change in the future, filling correct
+                        values here is a requirement.
+
+Timing properties for child nodes. All are optional and default to 0.
+
+ - gpmc,sync-clk:       Minimum clock period for synchronous mode, in picoseconds
+
+ Chip-select signal timings corresponding to GPMC_CONFIG2:
+ - gpmc,cs-on:          Assertion time
+ - gpmc,cs-rd-off:      Read deassertion time
+ - gpmc,cs-wr-off:      Write deassertion time
+
+ ADV signal timings corresponding to GPMC_CONFIG3:
+ - gpmc,adv-on:         Assertion time
+ - gpmc,adv-rd-off:     Read deassertion time
+ - gpmc,adv-wr-off:     Write deassertion time
+
+ WE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,we-on:          Assertion time
+ - gpmc,we-off:         Deassertion time
+
+ OE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,oe-on:          Assertion time
+ - gpmc,oe-off:         Deassertion time
+
+ Access time and cycle time timings corresponding to GPMC_CONFIG5:
+ - gpmc,page-burst-access: Multiple access word delay
+ - gpmc,access:         Start-cycle to first data valid delay
+ - gpmc,rd-cycle:       Total read cycle time
+ - gpmc,wr-cycle:       Total write cycle time
+
+The following are only applicable to OMAP3+ and AM335x:
+ - gpmc,wr-access
+ - gpmc,wr-data-mux-bus
+
+
+Example for an AM33xx board:
+
+        gpmc: gpmc@50000000 {
+                compatible = "ti,am3352-gpmc";
+                ti,hwmods = "gpmc";
+                reg = <0x50000000 0x2000>;
+                interrupts = <100>;
+
+                gpmc,num-cs = <8>;
+                gpmc,num-waitpins = <2>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
+
+                /* child nodes go here */
+        };
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
new file mode 100644
index 000000000000..9f464f906ffb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -0,0 +1,76 @@
+Device tree bindings for GPMC connected NANDs
+
+GPMC connected NAND (found on OMAP boards) are represented as child nodes of
+the GPMC controller with a name of "nand".
+
+All timing relevant properties as well as generic gpmc child properties are
+explained in a separate documents - please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+For NAND specific properties such as ECC modes or bus width, please refer to
+Documentation/devicetree/bindings/mtd/nand.txt
+
+
+Required properties:
+
+ - reg:         The CS line the peripheral is connected to
+
+Optional properties:
+
+ - nand-bus-width:              Set this numeric value to 16 if the hardware
+                                is wired that way. If not specified, a bus
+                                width of 8 is assumed.
+
+ - ti,nand-ecc-opt:             A string setting the ECC layout to use. One of:
+
+                "sw"            Software method (default)
+                "hw"            Hardware method
+                "hw-romcode"    gpmc hamming mode method & romcode layout
+                "bch4"          4-bit BCH ecc code
+                "bch8"          8-bit BCH ecc code
+
+For inline partiton table parsing (optional):
+
+ - #address-cells: should be set to 1
+ - #size-cells: should be set to 1
+
+Example for an AM33xx board:
+
+        gpmc: gpmc@50000000 {
+                compatible = "ti,am3352-gpmc";
+                ti,hwmods = "gpmc";
+                reg = <0x50000000 0x1000000>;
+                interrupts = <100>;
+                gpmc,num-cs = <8>;
+                gpmc,num-waitpins = <2>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x08000000 0x2000>;       /* CS0: NAND */
+
+                nand@0,0 {
+                        reg = <0 0 0>; /* CS0, offset 0 */
+                        nand-bus-width = <16>;
+                        ti,nand-ecc-opt = "bch8";
+
+                        gpmc,sync-clk = <0>;
+                        gpmc,cs-on = <0>;
+                        gpmc,cs-rd-off = <44>;
+                        gpmc,cs-wr-off = <44>;
+                        gpmc,adv-on = <6>;
+                        gpmc,adv-rd-off = <34>;
+                        gpmc,adv-wr-off = <44>;
+                        gpmc,we-off = <40>;
+                        gpmc,oe-off = <54>;
+                        gpmc,access = <64>;
+                        gpmc,rd-cycle = <82>;
+                        gpmc,wr-cycle = <82>;
+                        gpmc,wr-access = <40>;
+                        gpmc,wr-data-mux-bus = <0>;
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        /* partitions go here */
+                };
+        };
+