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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 00:02:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 00:02:35 -0400
commit367069f16e32e188d4687fe2c3e30f2ca583836f (patch)
tree977f87038b75e53af9d132cba2f7a2aecb2fa005 /Documentation/devicetree
parent81a3c10ce8a7fd5bf9a06bfc38bd417512911831 (diff)
parentc72dbae971400e466ad9ff16c920cd6d9d8c55a1 (diff)
Merge branch 'next/dt' of git://git.linaro.org/people/arnd/arm-soc
* 'next/dt' of git://git.linaro.org/people/arnd/arm-soc: ARM: gic: use module.h instead of export.h ARM: gic: fix irq_alloc_descs handling for sparse irq ARM: gic: add OF based initialization ARM: gic: add irq_domain support irq: support domains with non-zero hwirq base of/irq: introduce of_irq_init ARM: at91: add at91sam9g20 and Calao USB A9G20 DT support ARM: at91: dt: at91sam9g45 family and board device tree files arm/mx5: add device tree support for imx51 babbage arm/mx5: add device tree support for imx53 boards ARM: msm: Add devicetree support for msm8660-surf msm_serial: Add devicetree support msm_serial: Use relative resources for iomem Fix up conflicts in arch/arm/mach-at91/{at91sam9260.c,at91sam9g45.c}
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt19
-rw-r--r--Documentation/devicetree/bindings/arm/gic.txt55
-rw-r--r--Documentation/devicetree/bindings/tty/serial/msm_serial.txt27
3 files changed, 101 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
new file mode 100644
index 000000000000..e2401cd632ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -0,0 +1,19 @@
1i.MX51 Babbage Board
2Required root node properties:
3 - compatible = "fsl,imx51-babbage", "fsl,imx51";
4
5i.MX53 Automotive Reference Design Board
6Required root node properties:
7 - compatible = "fsl,imx53-ard", "fsl,imx53";
8
9i.MX53 Evaluation Kit
10Required root node properties:
11 - compatible = "fsl,imx53-evk", "fsl,imx53";
12
13i.MX53 Quick Start Board
14Required root node properties:
15 - compatible = "fsl,imx53-qsb", "fsl,imx53";
16
17i.MX53 Smart Mobile Reference Design Board
18Required root node properties:
19 - compatible = "fsl,imx53-smd", "fsl,imx53";
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
new file mode 100644
index 000000000000..52916b4aa1fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -0,0 +1,55 @@
1* ARM Generic Interrupt Controller
2
3ARM SMP cores are often associated with a GIC, providing per processor
4interrupts (PPI), shared processor interrupts (SPI) and software
5generated interrupts (SGI).
6
7Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8Secondary GICs are cascaded into the upward interrupt controller and do not
9have PPIs or SGIs.
10
11Main node required properties:
12
13- compatible : should be one of:
14 "arm,cortex-a9-gic"
15 "arm,arm11mp-gic"
16- interrupt-controller : Identifies the node as an interrupt controller
17- #interrupt-cells : Specifies the number of cells needed to encode an
18 interrupt source. The type shall be a <u32> and the value shall be 3.
19
20 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
21 interrupts.
22
23 The 2nd cell contains the interrupt number for the interrupt type.
24 SPI interrupts are in the range [0-987]. PPI interrupts are in the
25 range [0-15].
26
27 The 3rd cell is the flags, encoded as follows:
28 bits[3:0] trigger type and level flags.
29 1 = low-to-high edge triggered
30 2 = high-to-low edge triggered
31 4 = active high level-sensitive
32 8 = active low level-sensitive
33 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
34 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
35 the interrupt is wired to that CPU. Only valid for PPI interrupts.
36
37- reg : Specifies base physical address(s) and size of the GIC registers. The
38 first region is the GIC distributor register base and size. The 2nd region is
39 the GIC cpu interface register base and size.
40
41Optional
42- interrupts : Interrupt source of the parent interrupt controller. Only
43 present on secondary GICs.
44
45Example:
46
47 intc: interrupt-controller@fff11000 {
48 compatible = "arm,cortex-a9-gic";
49 #interrupt-cells = <3>;
50 #address-cells = <1>;
51 interrupt-controller;
52 reg = <0xfff11000 0x1000>,
53 <0xfff10100 0x100>;
54 };
55
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
new file mode 100644
index 000000000000..aef383eb8876
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
@@ -0,0 +1,27 @@
1* Qualcomm MSM UART
2
3Required properties:
4- compatible :
5 - "qcom,msm-uart", and one of "qcom,msm-hsuart" or
6 "qcom,msm-lsuart".
7- reg : offset and length of the register set for the device
8 for the hsuart operating in compatible mode, there should be a
9 second pair describing the gsbi registers.
10- interrupts : should contain the uart interrupt.
11
12There are two different UART blocks used in MSM devices,
13"qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is
14able to handle both of these, and matches against the "qcom,msm-uart"
15as the compatibility.
16
17The registers for the "qcom,msm-hsuart" device need to specify both
18register blocks, even for the common driver.
19
20Example:
21
22 uart@19c400000 {
23 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
24 reg = <0x19c40000 0x1000>,
25 <0x19c00000 0x1000>;
26 interrupts = <195>;
27 };