diff options
author | Tomasz Figa <t.figa@samsung.com> | 2013-04-23 11:46:22 -0400 |
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committer | Olof Johansson <olof@lixom.net> | 2013-04-28 15:16:03 -0400 |
commit | 5b5ff97d2c46c52d2a86208509633230c9a486ec (patch) | |
tree | 3e808242cb7e75db9942b817c73011bbf11dcb58 /Documentation/devicetree | |
parent | f11899894c0a683c754ca71b45f7c9c3d35a3a1c (diff) |
Documentation: Add device tree bindings for Samsung PWM timers
This patch adds missing documentation describing Device Tree bindings
for Samsung PWM timers.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/pwm/pwm-samsung.txt | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt new file mode 100644 index 000000000000..ac67c687a327 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt | |||
@@ -0,0 +1,43 @@ | |||
1 | * Samsung PWM timers | ||
2 | |||
3 | Samsung SoCs contain PWM timer blocks which can be used for system clock source | ||
4 | and clock event timers, as well as to drive SoC outputs with PWM signal. Each | ||
5 | PWM timer block provides 5 PWM channels (not all of them can drive physical | ||
6 | outputs - see SoC and board manual). | ||
7 | |||
8 | Be aware that the clocksource driver supports only uniprocessor systems. | ||
9 | |||
10 | Required properties: | ||
11 | - compatible : should be one of following: | ||
12 | samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs | ||
13 | samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs | ||
14 | samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs | ||
15 | samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, | ||
16 | Exynos4210 rev0 SoCs | ||
17 | samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, | ||
18 | Exynos4x12 and Exynos5250 SoCs | ||
19 | - reg: base address and size of register area | ||
20 | - interrupts: list of timer interrupts (one interrupt per timer, starting at | ||
21 | timer 0) | ||
22 | - #pwm-cells: number of cells used for PWM specifier - must be 3 | ||
23 | the specifier format is as follows: | ||
24 | - phandle to PWM controller node | ||
25 | - index of PWM channel (from 0 to 4) | ||
26 | - PWM signal period in nanoseconds | ||
27 | - bitmask of optional PWM flags: | ||
28 | 0x1 - invert PWM signal | ||
29 | |||
30 | Optional properties: | ||
31 | - samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular | ||
32 | platform - an array of up to 5 elements being indices of PWM channels | ||
33 | (from 0 to 4), the order does not matter. | ||
34 | |||
35 | Example: | ||
36 | pwm@7f006000 { | ||
37 | compatible = "samsung,s3c6400-pwm"; | ||
38 | reg = <0x7f006000 0x1000>; | ||
39 | interrupt-parent = <&vic0>; | ||
40 | interrupts = <23>, <24>, <25>, <27>, <28>; | ||
41 | samsung,pwm-outputs = <0>, <1>; | ||
42 | #pwm-cells = <3>; | ||
43 | } | ||