diff options
author | Kyle Moffett <Kyle.D.Moffett@boeing.com> | 2011-12-22 05:19:13 -0500 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-02-22 18:50:00 -0500 |
commit | c1b8d45db4dbc64cc6015f97922f767fdf782f64 (patch) | |
tree | c23f986f6601b2f67645eca5b8744c8d753bc094 /Documentation/devicetree/bindings | |
parent | 5019609fce965dbdc66a7d947385fe92ca522231 (diff) |
powerpc/mpic: Add "last-interrupt-source" property to override hardware
The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not
correctly report the number of hardware interrupt sources, so software
needs to override the detected value with "256".
To avoid needing to write custom board-specific code to detect that
scenario, allow it to be easily overridden in the device-tree.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt index b393ccf1e9f3..dc5744636a57 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |||
@@ -70,6 +70,13 @@ PROPERTIES | |||
70 | If present the MPIC will be assumed to only be able to route | 70 | If present the MPIC will be assumed to only be able to route |
71 | non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). | 71 | non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). |
72 | 72 | ||
73 | - last-interrupt-source | ||
74 | Usage: optional | ||
75 | Value type: <u32> | ||
76 | Some MPICs do not correctly report the number of hardware sources | ||
77 | in the global feature registers. If specified, this field will | ||
78 | override the value read from MPIC_GREG_FEATURE_LAST_SRC. | ||
79 | |||
73 | INTERRUPT SPECIFIER DEFINITION | 80 | INTERRUPT SPECIFIER DEFINITION |
74 | 81 | ||
75 | Interrupt specifiers consists of 4 cells encoded as | 82 | Interrupt specifiers consists of 4 cells encoded as |