diff options
author | Grant Likely <grant.likely@secretlab.ca> | 2011-01-26 12:10:40 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2011-01-31 02:09:01 -0500 |
commit | d524dac9279b6a41ffdf7ff7958c577f2e387db6 (patch) | |
tree | 294166d18a1c89c4cebb2571ea7b124876fb01ef /Documentation/devicetree/bindings | |
parent | 1bae4ce27c9c90344f23c65ea6966c50ffeae2f5 (diff) |
dt: Move device tree documentation out of powerpc directory
The device tree is used by more than just PowerPC. Make the documentation
directory available to all.
v2: reorganized files while moving to create arch and driver specific
directories.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'Documentation/devicetree/bindings')
59 files changed, 4107 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt new file mode 100644 index 000000000000..b46bcf46c3d8 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/fsl-sata.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | * Freescale 8xxx/3.0 Gb/s SATA nodes | ||
2 | |||
3 | SATA nodes are defined to describe on-chip Serial ATA controllers. | ||
4 | Each SATA port should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, contains 2 entries, first is | ||
8 | "fsl,CHIP-sata", where CHIP is the processor | ||
9 | (mpc8315, mpc8379, etc.) and the second is | ||
10 | "fsl,pq-sata" | ||
11 | - interrupts : <interrupt mapping for SATA IRQ> | ||
12 | - cell-index : controller index. | ||
13 | 1 for controller @ 0x18000 | ||
14 | 2 for controller @ 0x19000 | ||
15 | 3 for controller @ 0x1a000 | ||
16 | 4 for controller @ 0x1b000 | ||
17 | |||
18 | Optional properties: | ||
19 | - interrupt-parent : optional, if needed for interrupt mapping | ||
20 | - reg : <registers mapping> | ||
21 | |||
22 | Example: | ||
23 | sata@18000 { | ||
24 | compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; | ||
25 | reg = <0x18000 0x1000>; | ||
26 | cell-index = <1>; | ||
27 | interrupts = <2c 8>; | ||
28 | interrupt-parent = < &ipic >; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/eeprom.txt b/Documentation/devicetree/bindings/eeprom.txt new file mode 100644 index 000000000000..4342c10de1bf --- /dev/null +++ b/Documentation/devicetree/bindings/eeprom.txt | |||
@@ -0,0 +1,28 @@ | |||
1 | EEPROMs (I2C) | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "<manufacturer>,<type>" | ||
6 | If there is no specific driver for <manufacturer>, a generic | ||
7 | driver based on <type> is selected. Possible types are: | ||
8 | 24c00, 24c01, 24c02, 24c04, 24c08, 24c16, 24c32, 24c64, | ||
9 | 24c128, 24c256, 24c512, 24c1024, spd | ||
10 | |||
11 | - reg : the I2C address of the EEPROM | ||
12 | |||
13 | Optional properties: | ||
14 | |||
15 | - pagesize : the length of the pagesize for writing. Please consult the | ||
16 | manual of your device, that value varies a lot. A wrong value | ||
17 | may result in data loss! If not specified, a safety value of | ||
18 | '1' is used which will be very slow. | ||
19 | |||
20 | - read-only: this parameterless property disables writes to the eeprom | ||
21 | |||
22 | Example: | ||
23 | |||
24 | eeprom@52 { | ||
25 | compatible = "atmel,24c32"; | ||
26 | reg = <0x52>; | ||
27 | pagesize = <32>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt new file mode 100644 index 000000000000..b0019eb5330e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt | |||
@@ -0,0 +1,60 @@ | |||
1 | GPIO controllers on MPC8xxx SoCs | ||
2 | |||
3 | This is for the non-QE/CPM/GUTs GPIO controllers as found on | ||
4 | 8349, 8572, 8610 and compatible. | ||
5 | |||
6 | Every GPIO controller node must have #gpio-cells property defined, | ||
7 | this information will be used to translate gpio-specifiers. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for | ||
11 | 83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx. | ||
12 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
13 | second cell is used to specify optional parameters (currently unused). | ||
14 | - interrupts : Interrupt mapping for GPIO IRQ. | ||
15 | - interrupt-parent : Phandle for the interrupt controller that | ||
16 | services interrupts for this device. | ||
17 | - gpio-controller : Marks the port as GPIO controller. | ||
18 | |||
19 | Example of gpio-controller nodes for a MPC8347 SoC: | ||
20 | |||
21 | gpio1: gpio-controller@c00 { | ||
22 | #gpio-cells = <2>; | ||
23 | compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | ||
24 | reg = <0xc00 0x100>; | ||
25 | interrupts = <74 0x8>; | ||
26 | interrupt-parent = <&ipic>; | ||
27 | gpio-controller; | ||
28 | }; | ||
29 | |||
30 | gpio2: gpio-controller@d00 { | ||
31 | #gpio-cells = <2>; | ||
32 | compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | ||
33 | reg = <0xd00 0x100>; | ||
34 | interrupts = <75 0x8>; | ||
35 | interrupt-parent = <&ipic>; | ||
36 | gpio-controller; | ||
37 | }; | ||
38 | |||
39 | See booting-without-of.txt for details of how to specify GPIO | ||
40 | information for devices. | ||
41 | |||
42 | To use GPIO pins as interrupt sources for peripherals, specify the | ||
43 | GPIO controller as the interrupt parent and define GPIO number + | ||
44 | trigger mode using the interrupts property, which is defined like | ||
45 | this: | ||
46 | |||
47 | interrupts = <number trigger>, where: | ||
48 | - number: GPIO pin (0..31) | ||
49 | - trigger: trigger mode: | ||
50 | 2 = trigger on falling edge | ||
51 | 3 = trigger on both edges | ||
52 | |||
53 | Example of device using this is: | ||
54 | |||
55 | funkyfpga@0 { | ||
56 | compatible = "funky-fpga"; | ||
57 | ... | ||
58 | interrupts = <4 3>; | ||
59 | interrupt-parent = <&gpio1>; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt new file mode 100644 index 000000000000..edaa84d288a1 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -0,0 +1,50 @@ | |||
1 | Specifying GPIO information for devices | ||
2 | ============================================ | ||
3 | |||
4 | 1) gpios property | ||
5 | ----------------- | ||
6 | |||
7 | Nodes that makes use of GPIOs should define them using `gpios' property, | ||
8 | format of which is: <&gpio-controller1-phandle gpio1-specifier | ||
9 | &gpio-controller2-phandle gpio2-specifier | ||
10 | 0 /* holes are permitted, means no GPIO 3 */ | ||
11 | &gpio-controller4-phandle gpio4-specifier | ||
12 | ...>; | ||
13 | |||
14 | Note that gpio-specifier length is controller dependent. | ||
15 | |||
16 | gpio-specifier may encode: bank, pin position inside the bank, | ||
17 | whether pin is open-drain and whether pin is logically inverted. | ||
18 | |||
19 | Example of the node using GPIOs: | ||
20 | |||
21 | node { | ||
22 | gpios = <&qe_pio_e 18 0>; | ||
23 | }; | ||
24 | |||
25 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | ||
26 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. | ||
27 | |||
28 | 2) gpio-controller nodes | ||
29 | ------------------------ | ||
30 | |||
31 | Every GPIO controller node must have #gpio-cells property defined, | ||
32 | this information will be used to translate gpio-specifiers. | ||
33 | |||
34 | Example of two SOC GPIO banks defined as gpio-controller nodes: | ||
35 | |||
36 | qe_pio_a: gpio-controller@1400 { | ||
37 | #gpio-cells = <2>; | ||
38 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; | ||
39 | reg = <0x1400 0x18>; | ||
40 | gpio-controller; | ||
41 | }; | ||
42 | |||
43 | qe_pio_e: gpio-controller@1460 { | ||
44 | #gpio-cells = <2>; | ||
45 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | ||
46 | reg = <0x1460 0x18>; | ||
47 | gpio-controller; | ||
48 | }; | ||
49 | |||
50 | |||
diff --git a/Documentation/devicetree/bindings/gpio/led.txt b/Documentation/devicetree/bindings/gpio/led.txt new file mode 100644 index 000000000000..064db928c3c1 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/led.txt | |||
@@ -0,0 +1,58 @@ | |||
1 | LEDs connected to GPIO lines | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "gpio-leds". | ||
5 | |||
6 | Each LED is represented as a sub-node of the gpio-leds device. Each | ||
7 | node's name represents the name of the corresponding LED. | ||
8 | |||
9 | LED sub-node properties: | ||
10 | - gpios : Should specify the LED's GPIO, see "Specifying GPIO information | ||
11 | for devices" in Documentation/powerpc/booting-without-of.txt. Active | ||
12 | low LEDs should be indicated using flags in the GPIO specifier. | ||
13 | - label : (optional) The label for this LED. If omitted, the label is | ||
14 | taken from the node name (excluding the unit address). | ||
15 | - linux,default-trigger : (optional) This parameter, if present, is a | ||
16 | string defining the trigger assigned to the LED. Current triggers are: | ||
17 | "backlight" - LED will act as a back-light, controlled by the framebuffer | ||
18 | system | ||
19 | "default-on" - LED will turn on, but see "default-state" below | ||
20 | "heartbeat" - LED "double" flashes at a load average based rate | ||
21 | "ide-disk" - LED indicates disk activity | ||
22 | "timer" - LED flashes at a fixed, configurable rate | ||
23 | - default-state: (optional) The initial state of the LED. Valid | ||
24 | values are "on", "off", and "keep". If the LED is already on or off | ||
25 | and the default-state property is set the to same value, then no | ||
26 | glitch should be produced where the LED momentarily turns off (or | ||
27 | on). The "keep" setting will keep the LED at whatever its current | ||
28 | state is, without producing a glitch. The default is off if this | ||
29 | property is not present. | ||
30 | |||
31 | Examples: | ||
32 | |||
33 | leds { | ||
34 | compatible = "gpio-leds"; | ||
35 | hdd { | ||
36 | label = "IDE Activity"; | ||
37 | gpios = <&mcu_pio 0 1>; /* Active low */ | ||
38 | linux,default-trigger = "ide-disk"; | ||
39 | }; | ||
40 | |||
41 | fault { | ||
42 | gpios = <&mcu_pio 1 0>; | ||
43 | /* Keep LED on if BIOS detected hardware fault */ | ||
44 | default-state = "keep"; | ||
45 | }; | ||
46 | }; | ||
47 | |||
48 | run-control { | ||
49 | compatible = "gpio-leds"; | ||
50 | red { | ||
51 | gpios = <&mpc8572 6 0>; | ||
52 | default-state = "off"; | ||
53 | }; | ||
54 | green { | ||
55 | gpios = <&mpc8572 7 0>; | ||
56 | default-state = "on"; | ||
57 | }; | ||
58 | } | ||
diff --git a/Documentation/devicetree/bindings/i2c/fsl-i2c.txt b/Documentation/devicetree/bindings/i2c/fsl-i2c.txt new file mode 100644 index 000000000000..1eacd6b20ed5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/fsl-i2c.txt | |||
@@ -0,0 +1,64 @@ | |||
1 | * I2C | ||
2 | |||
3 | Required properties : | ||
4 | |||
5 | - reg : Offset and length of the register set for the device | ||
6 | - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a | ||
7 | compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121, | ||
8 | mpc5200 or mpc5200b. For the mpc5121, an additional node | ||
9 | "fsl,mpc5121-i2c-ctrl" is required as shown in the example below. | ||
10 | |||
11 | Recommended properties : | ||
12 | |||
13 | - interrupts : <a b> where a is the interrupt number and b is a | ||
14 | field that represents an encoding of the sense and level | ||
15 | information for the interrupt. This should be encoded based on | ||
16 | the information in section 2) depending on the type of interrupt | ||
17 | controller you have. | ||
18 | - interrupt-parent : the phandle for the interrupt controller that | ||
19 | services interrupts for this device. | ||
20 | - fsl,preserve-clocking : boolean; if defined, the clock settings | ||
21 | from the bootloader are preserved (not touched). | ||
22 | - clock-frequency : desired I2C bus clock frequency in Hz. | ||
23 | - fsl,timeout : I2C bus timeout in microseconds. | ||
24 | |||
25 | Examples : | ||
26 | |||
27 | /* MPC5121 based board */ | ||
28 | i2c@1740 { | ||
29 | #address-cells = <1>; | ||
30 | #size-cells = <0>; | ||
31 | compatible = "fsl,mpc5121-i2c", "fsl-i2c"; | ||
32 | reg = <0x1740 0x20>; | ||
33 | interrupts = <11 0x8>; | ||
34 | interrupt-parent = <&ipic>; | ||
35 | clock-frequency = <100000>; | ||
36 | }; | ||
37 | |||
38 | i2ccontrol@1760 { | ||
39 | compatible = "fsl,mpc5121-i2c-ctrl"; | ||
40 | reg = <0x1760 0x8>; | ||
41 | }; | ||
42 | |||
43 | /* MPC5200B based board */ | ||
44 | i2c@3d00 { | ||
45 | #address-cells = <1>; | ||
46 | #size-cells = <0>; | ||
47 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | ||
48 | reg = <0x3d00 0x40>; | ||
49 | interrupts = <2 15 0>; | ||
50 | interrupt-parent = <&mpc5200_pic>; | ||
51 | fsl,preserve-clocking; | ||
52 | }; | ||
53 | |||
54 | /* MPC8544 base board */ | ||
55 | i2c@3100 { | ||
56 | #address-cells = <1>; | ||
57 | #size-cells = <0>; | ||
58 | compatible = "fsl,mpc8544-i2c", "fsl-i2c"; | ||
59 | reg = <0x3100 0x100>; | ||
60 | interrupts = <43 2>; | ||
61 | interrupt-parent = <&mpic>; | ||
62 | clock-frequency = <400000>; | ||
63 | fsl,timeout = <10000>; | ||
64 | }; | ||
diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt new file mode 100644 index 000000000000..f1533d91953a --- /dev/null +++ b/Documentation/devicetree/bindings/marvell.txt | |||
@@ -0,0 +1,521 @@ | |||
1 | Marvell Discovery mv64[345]6x System Controller chips | ||
2 | =========================================================== | ||
3 | |||
4 | The Marvell mv64[345]60 series of system controller chips contain | ||
5 | many of the peripherals needed to implement a complete computer | ||
6 | system. In this section, we define device tree nodes to describe | ||
7 | the system controller chip itself and each of the peripherals | ||
8 | which it contains. Compatible string values for each node are | ||
9 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | ||
10 | |||
11 | 1) The /system-controller node | ||
12 | |||
13 | This node is used to represent the system-controller and must be | ||
14 | present when the system uses a system controller chip. The top-level | ||
15 | system-controller node contains information that is global to all | ||
16 | devices within the system controller chip. The node name begins | ||
17 | with "system-controller" followed by the unit address, which is | ||
18 | the base address of the memory-mapped register set for the system | ||
19 | controller chip. | ||
20 | |||
21 | Required properties: | ||
22 | |||
23 | - ranges : Describes the translation of system controller addresses | ||
24 | for memory mapped registers. | ||
25 | - clock-frequency: Contains the main clock frequency for the system | ||
26 | controller chip. | ||
27 | - reg : This property defines the address and size of the | ||
28 | memory-mapped registers contained within the system controller | ||
29 | chip. The address specified in the "reg" property should match | ||
30 | the unit address of the system-controller node. | ||
31 | - #address-cells : Address representation for system controller | ||
32 | devices. This field represents the number of cells needed to | ||
33 | represent the address of the memory-mapped registers of devices | ||
34 | within the system controller chip. | ||
35 | - #size-cells : Size representation for the memory-mapped | ||
36 | registers within the system controller chip. | ||
37 | - #interrupt-cells : Defines the width of cells used to represent | ||
38 | interrupts. | ||
39 | |||
40 | Optional properties: | ||
41 | |||
42 | - model : The specific model of the system controller chip. Such | ||
43 | as, "mv64360", "mv64460", or "mv64560". | ||
44 | - compatible : A string identifying the compatibility identifiers | ||
45 | of the system controller chip. | ||
46 | |||
47 | The system-controller node contains child nodes for each system | ||
48 | controller device that the platform uses. Nodes should not be created | ||
49 | for devices which exist on the system controller chip but are not used | ||
50 | |||
51 | Example Marvell Discovery mv64360 system-controller node: | ||
52 | |||
53 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | ||
54 | #address-cells = <1>; | ||
55 | #size-cells = <1>; | ||
56 | model = "mv64360"; /* Default */ | ||
57 | compatible = "marvell,mv64360"; | ||
58 | clock-frequency = <133333333>; | ||
59 | reg = <0xf1000000 0x10000>; | ||
60 | virtual-reg = <0xf1000000>; | ||
61 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | ||
62 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | ||
63 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | ||
64 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | ||
65 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | ||
66 | |||
67 | [ child node definitions... ] | ||
68 | } | ||
69 | |||
70 | 2) Child nodes of /system-controller | ||
71 | |||
72 | a) Marvell Discovery MDIO bus | ||
73 | |||
74 | The MDIO is a bus to which the PHY devices are connected. For each | ||
75 | device that exists on this bus, a child node should be created. See | ||
76 | the definition of the PHY node below for an example of how to define | ||
77 | a PHY. | ||
78 | |||
79 | Required properties: | ||
80 | - #address-cells : Should be <1> | ||
81 | - #size-cells : Should be <0> | ||
82 | - device_type : Should be "mdio" | ||
83 | - compatible : Should be "marvell,mv64360-mdio" | ||
84 | |||
85 | Example: | ||
86 | |||
87 | mdio { | ||
88 | #address-cells = <1>; | ||
89 | #size-cells = <0>; | ||
90 | device_type = "mdio"; | ||
91 | compatible = "marvell,mv64360-mdio"; | ||
92 | |||
93 | ethernet-phy@0 { | ||
94 | ...... | ||
95 | }; | ||
96 | }; | ||
97 | |||
98 | |||
99 | b) Marvell Discovery ethernet controller | ||
100 | |||
101 | The Discover ethernet controller is described with two levels | ||
102 | of nodes. The first level describes an ethernet silicon block | ||
103 | and the second level describes up to 3 ethernet nodes within | ||
104 | that block. The reason for the multiple levels is that the | ||
105 | registers for the node are interleaved within a single set | ||
106 | of registers. The "ethernet-block" level describes the | ||
107 | shared register set, and the "ethernet" nodes describe ethernet | ||
108 | port-specific properties. | ||
109 | |||
110 | Ethernet block node | ||
111 | |||
112 | Required properties: | ||
113 | - #address-cells : <1> | ||
114 | - #size-cells : <0> | ||
115 | - compatible : "marvell,mv64360-eth-block" | ||
116 | - reg : Offset and length of the register set for this block | ||
117 | |||
118 | Example Discovery Ethernet block node: | ||
119 | ethernet-block@2000 { | ||
120 | #address-cells = <1>; | ||
121 | #size-cells = <0>; | ||
122 | compatible = "marvell,mv64360-eth-block"; | ||
123 | reg = <0x2000 0x2000>; | ||
124 | ethernet@0 { | ||
125 | ....... | ||
126 | }; | ||
127 | }; | ||
128 | |||
129 | Ethernet port node | ||
130 | |||
131 | Required properties: | ||
132 | - device_type : Should be "network". | ||
133 | - compatible : Should be "marvell,mv64360-eth". | ||
134 | - reg : Should be <0>, <1>, or <2>, according to which registers | ||
135 | within the silicon block the device uses. | ||
136 | - interrupts : <a> where a is the interrupt number for the port. | ||
137 | - interrupt-parent : the phandle for the interrupt controller | ||
138 | that services interrupts for this device. | ||
139 | - phy : the phandle for the PHY connected to this ethernet | ||
140 | controller. | ||
141 | - local-mac-address : 6 bytes, MAC address | ||
142 | |||
143 | Example Discovery Ethernet port node: | ||
144 | ethernet@0 { | ||
145 | device_type = "network"; | ||
146 | compatible = "marvell,mv64360-eth"; | ||
147 | reg = <0>; | ||
148 | interrupts = <32>; | ||
149 | interrupt-parent = <&PIC>; | ||
150 | phy = <&PHY0>; | ||
151 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
152 | }; | ||
153 | |||
154 | |||
155 | |||
156 | c) Marvell Discovery PHY nodes | ||
157 | |||
158 | Required properties: | ||
159 | - device_type : Should be "ethernet-phy" | ||
160 | - interrupts : <a> where a is the interrupt number for this phy. | ||
161 | - interrupt-parent : the phandle for the interrupt controller that | ||
162 | services interrupts for this device. | ||
163 | - reg : The ID number for the phy, usually a small integer | ||
164 | |||
165 | Example Discovery PHY node: | ||
166 | ethernet-phy@1 { | ||
167 | device_type = "ethernet-phy"; | ||
168 | compatible = "broadcom,bcm5421"; | ||
169 | interrupts = <76>; /* GPP 12 */ | ||
170 | interrupt-parent = <&PIC>; | ||
171 | reg = <1>; | ||
172 | }; | ||
173 | |||
174 | |||
175 | d) Marvell Discovery SDMA nodes | ||
176 | |||
177 | Represent DMA hardware associated with the MPSC (multiprotocol | ||
178 | serial controllers). | ||
179 | |||
180 | Required properties: | ||
181 | - compatible : "marvell,mv64360-sdma" | ||
182 | - reg : Offset and length of the register set for this device | ||
183 | - interrupts : <a> where a is the interrupt number for the DMA | ||
184 | device. | ||
185 | - interrupt-parent : the phandle for the interrupt controller | ||
186 | that services interrupts for this device. | ||
187 | |||
188 | Example Discovery SDMA node: | ||
189 | sdma@4000 { | ||
190 | compatible = "marvell,mv64360-sdma"; | ||
191 | reg = <0x4000 0xc18>; | ||
192 | virtual-reg = <0xf1004000>; | ||
193 | interrupts = <36>; | ||
194 | interrupt-parent = <&PIC>; | ||
195 | }; | ||
196 | |||
197 | |||
198 | e) Marvell Discovery BRG nodes | ||
199 | |||
200 | Represent baud rate generator hardware associated with the MPSC | ||
201 | (multiprotocol serial controllers). | ||
202 | |||
203 | Required properties: | ||
204 | - compatible : "marvell,mv64360-brg" | ||
205 | - reg : Offset and length of the register set for this device | ||
206 | - clock-src : A value from 0 to 15 which selects the clock | ||
207 | source for the baud rate generator. This value corresponds | ||
208 | to the CLKS value in the BRGx configuration register. See | ||
209 | the mv64x60 User's Manual. | ||
210 | - clock-frequence : The frequency (in Hz) of the baud rate | ||
211 | generator's input clock. | ||
212 | - current-speed : The current speed setting (presumably by | ||
213 | firmware) of the baud rate generator. | ||
214 | |||
215 | Example Discovery BRG node: | ||
216 | brg@b200 { | ||
217 | compatible = "marvell,mv64360-brg"; | ||
218 | reg = <0xb200 0x8>; | ||
219 | clock-src = <8>; | ||
220 | clock-frequency = <133333333>; | ||
221 | current-speed = <9600>; | ||
222 | }; | ||
223 | |||
224 | |||
225 | f) Marvell Discovery CUNIT nodes | ||
226 | |||
227 | Represent the Serial Communications Unit device hardware. | ||
228 | |||
229 | Required properties: | ||
230 | - reg : Offset and length of the register set for this device | ||
231 | |||
232 | Example Discovery CUNIT node: | ||
233 | cunit@f200 { | ||
234 | reg = <0xf200 0x200>; | ||
235 | }; | ||
236 | |||
237 | |||
238 | g) Marvell Discovery MPSCROUTING nodes | ||
239 | |||
240 | Represent the Discovery's MPSC routing hardware | ||
241 | |||
242 | Required properties: | ||
243 | - reg : Offset and length of the register set for this device | ||
244 | |||
245 | Example Discovery CUNIT node: | ||
246 | mpscrouting@b500 { | ||
247 | reg = <0xb400 0xc>; | ||
248 | }; | ||
249 | |||
250 | |||
251 | h) Marvell Discovery MPSCINTR nodes | ||
252 | |||
253 | Represent the Discovery's MPSC DMA interrupt hardware registers | ||
254 | (SDMA cause and mask registers). | ||
255 | |||
256 | Required properties: | ||
257 | - reg : Offset and length of the register set for this device | ||
258 | |||
259 | Example Discovery MPSCINTR node: | ||
260 | mpsintr@b800 { | ||
261 | reg = <0xb800 0x100>; | ||
262 | }; | ||
263 | |||
264 | |||
265 | i) Marvell Discovery MPSC nodes | ||
266 | |||
267 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | ||
268 | serial port. | ||
269 | |||
270 | Required properties: | ||
271 | - device_type : "serial" | ||
272 | - compatible : "marvell,mv64360-mpsc" | ||
273 | - reg : Offset and length of the register set for this device | ||
274 | - sdma : the phandle for the SDMA node used by this port | ||
275 | - brg : the phandle for the BRG node used by this port | ||
276 | - cunit : the phandle for the CUNIT node used by this port | ||
277 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | ||
278 | - mpscintr : the phandle for the MPSCINTR node used by this port | ||
279 | - cell-index : the hardware index of this cell in the MPSC core | ||
280 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | ||
281 | register | ||
282 | - interrupts : <a> where a is the interrupt number for the MPSC. | ||
283 | - interrupt-parent : the phandle for the interrupt controller | ||
284 | that services interrupts for this device. | ||
285 | |||
286 | Example Discovery MPSCINTR node: | ||
287 | mpsc@8000 { | ||
288 | device_type = "serial"; | ||
289 | compatible = "marvell,mv64360-mpsc"; | ||
290 | reg = <0x8000 0x38>; | ||
291 | virtual-reg = <0xf1008000>; | ||
292 | sdma = <&SDMA0>; | ||
293 | brg = <&BRG0>; | ||
294 | cunit = <&CUNIT>; | ||
295 | mpscrouting = <&MPSCROUTING>; | ||
296 | mpscintr = <&MPSCINTR>; | ||
297 | cell-index = <0>; | ||
298 | max_idle = <40>; | ||
299 | interrupts = <40>; | ||
300 | interrupt-parent = <&PIC>; | ||
301 | }; | ||
302 | |||
303 | |||
304 | j) Marvell Discovery Watch Dog Timer nodes | ||
305 | |||
306 | Represent the Discovery's watchdog timer hardware | ||
307 | |||
308 | Required properties: | ||
309 | - compatible : "marvell,mv64360-wdt" | ||
310 | - reg : Offset and length of the register set for this device | ||
311 | |||
312 | Example Discovery Watch Dog Timer node: | ||
313 | wdt@b410 { | ||
314 | compatible = "marvell,mv64360-wdt"; | ||
315 | reg = <0xb410 0x8>; | ||
316 | }; | ||
317 | |||
318 | |||
319 | k) Marvell Discovery I2C nodes | ||
320 | |||
321 | Represent the Discovery's I2C hardware | ||
322 | |||
323 | Required properties: | ||
324 | - device_type : "i2c" | ||
325 | - compatible : "marvell,mv64360-i2c" | ||
326 | - reg : Offset and length of the register set for this device | ||
327 | - interrupts : <a> where a is the interrupt number for the I2C. | ||
328 | - interrupt-parent : the phandle for the interrupt controller | ||
329 | that services interrupts for this device. | ||
330 | |||
331 | Example Discovery I2C node: | ||
332 | compatible = "marvell,mv64360-i2c"; | ||
333 | reg = <0xc000 0x20>; | ||
334 | virtual-reg = <0xf100c000>; | ||
335 | interrupts = <37>; | ||
336 | interrupt-parent = <&PIC>; | ||
337 | }; | ||
338 | |||
339 | |||
340 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | ||
341 | |||
342 | Represent the Discovery's PIC hardware | ||
343 | |||
344 | Required properties: | ||
345 | - #interrupt-cells : <1> | ||
346 | - #address-cells : <0> | ||
347 | - compatible : "marvell,mv64360-pic" | ||
348 | - reg : Offset and length of the register set for this device | ||
349 | - interrupt-controller | ||
350 | |||
351 | Example Discovery PIC node: | ||
352 | pic { | ||
353 | #interrupt-cells = <1>; | ||
354 | #address-cells = <0>; | ||
355 | compatible = "marvell,mv64360-pic"; | ||
356 | reg = <0x0 0x88>; | ||
357 | interrupt-controller; | ||
358 | }; | ||
359 | |||
360 | |||
361 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | ||
362 | |||
363 | Represent the Discovery's MPP hardware | ||
364 | |||
365 | Required properties: | ||
366 | - compatible : "marvell,mv64360-mpp" | ||
367 | - reg : Offset and length of the register set for this device | ||
368 | |||
369 | Example Discovery MPP node: | ||
370 | mpp@f000 { | ||
371 | compatible = "marvell,mv64360-mpp"; | ||
372 | reg = <0xf000 0x10>; | ||
373 | }; | ||
374 | |||
375 | |||
376 | n) Marvell Discovery GPP (General Purpose Pins) nodes | ||
377 | |||
378 | Represent the Discovery's GPP hardware | ||
379 | |||
380 | Required properties: | ||
381 | - compatible : "marvell,mv64360-gpp" | ||
382 | - reg : Offset and length of the register set for this device | ||
383 | |||
384 | Example Discovery GPP node: | ||
385 | gpp@f000 { | ||
386 | compatible = "marvell,mv64360-gpp"; | ||
387 | reg = <0xf100 0x20>; | ||
388 | }; | ||
389 | |||
390 | |||
391 | o) Marvell Discovery PCI host bridge node | ||
392 | |||
393 | Represents the Discovery's PCI host bridge device. The properties | ||
394 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | ||
395 | 1275-1994. A typical value for the compatible property is | ||
396 | "marvell,mv64360-pci". | ||
397 | |||
398 | Example Discovery PCI host bridge node | ||
399 | pci@80000000 { | ||
400 | #address-cells = <3>; | ||
401 | #size-cells = <2>; | ||
402 | #interrupt-cells = <1>; | ||
403 | device_type = "pci"; | ||
404 | compatible = "marvell,mv64360-pci"; | ||
405 | reg = <0xcf8 0x8>; | ||
406 | ranges = <0x01000000 0x0 0x0 | ||
407 | 0x88000000 0x0 0x01000000 | ||
408 | 0x02000000 0x0 0x80000000 | ||
409 | 0x80000000 0x0 0x08000000>; | ||
410 | bus-range = <0 255>; | ||
411 | clock-frequency = <66000000>; | ||
412 | interrupt-parent = <&PIC>; | ||
413 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
414 | interrupt-map = < | ||
415 | /* IDSEL 0x0a */ | ||
416 | 0x5000 0 0 1 &PIC 80 | ||
417 | 0x5000 0 0 2 &PIC 81 | ||
418 | 0x5000 0 0 3 &PIC 91 | ||
419 | 0x5000 0 0 4 &PIC 93 | ||
420 | |||
421 | /* IDSEL 0x0b */ | ||
422 | 0x5800 0 0 1 &PIC 91 | ||
423 | 0x5800 0 0 2 &PIC 93 | ||
424 | 0x5800 0 0 3 &PIC 80 | ||
425 | 0x5800 0 0 4 &PIC 81 | ||
426 | |||
427 | /* IDSEL 0x0c */ | ||
428 | 0x6000 0 0 1 &PIC 91 | ||
429 | 0x6000 0 0 2 &PIC 93 | ||
430 | 0x6000 0 0 3 &PIC 80 | ||
431 | 0x6000 0 0 4 &PIC 81 | ||
432 | |||
433 | /* IDSEL 0x0d */ | ||
434 | 0x6800 0 0 1 &PIC 93 | ||
435 | 0x6800 0 0 2 &PIC 80 | ||
436 | 0x6800 0 0 3 &PIC 81 | ||
437 | 0x6800 0 0 4 &PIC 91 | ||
438 | >; | ||
439 | }; | ||
440 | |||
441 | |||
442 | p) Marvell Discovery CPU Error nodes | ||
443 | |||
444 | Represent the Discovery's CPU error handler device. | ||
445 | |||
446 | Required properties: | ||
447 | - compatible : "marvell,mv64360-cpu-error" | ||
448 | - reg : Offset and length of the register set for this device | ||
449 | - interrupts : the interrupt number for this device | ||
450 | - interrupt-parent : the phandle for the interrupt controller | ||
451 | that services interrupts for this device. | ||
452 | |||
453 | Example Discovery CPU Error node: | ||
454 | cpu-error@0070 { | ||
455 | compatible = "marvell,mv64360-cpu-error"; | ||
456 | reg = <0x70 0x10 0x128 0x28>; | ||
457 | interrupts = <3>; | ||
458 | interrupt-parent = <&PIC>; | ||
459 | }; | ||
460 | |||
461 | |||
462 | q) Marvell Discovery SRAM Controller nodes | ||
463 | |||
464 | Represent the Discovery's SRAM controller device. | ||
465 | |||
466 | Required properties: | ||
467 | - compatible : "marvell,mv64360-sram-ctrl" | ||
468 | - reg : Offset and length of the register set for this device | ||
469 | - interrupts : the interrupt number for this device | ||
470 | - interrupt-parent : the phandle for the interrupt controller | ||
471 | that services interrupts for this device. | ||
472 | |||
473 | Example Discovery SRAM Controller node: | ||
474 | sram-ctrl@0380 { | ||
475 | compatible = "marvell,mv64360-sram-ctrl"; | ||
476 | reg = <0x380 0x80>; | ||
477 | interrupts = <13>; | ||
478 | interrupt-parent = <&PIC>; | ||
479 | }; | ||
480 | |||
481 | |||
482 | r) Marvell Discovery PCI Error Handler nodes | ||
483 | |||
484 | Represent the Discovery's PCI error handler device. | ||
485 | |||
486 | Required properties: | ||
487 | - compatible : "marvell,mv64360-pci-error" | ||
488 | - reg : Offset and length of the register set for this device | ||
489 | - interrupts : the interrupt number for this device | ||
490 | - interrupt-parent : the phandle for the interrupt controller | ||
491 | that services interrupts for this device. | ||
492 | |||
493 | Example Discovery PCI Error Handler node: | ||
494 | pci-error@1d40 { | ||
495 | compatible = "marvell,mv64360-pci-error"; | ||
496 | reg = <0x1d40 0x40 0xc28 0x4>; | ||
497 | interrupts = <12>; | ||
498 | interrupt-parent = <&PIC>; | ||
499 | }; | ||
500 | |||
501 | |||
502 | s) Marvell Discovery Memory Controller nodes | ||
503 | |||
504 | Represent the Discovery's memory controller device. | ||
505 | |||
506 | Required properties: | ||
507 | - compatible : "marvell,mv64360-mem-ctrl" | ||
508 | - reg : Offset and length of the register set for this device | ||
509 | - interrupts : the interrupt number for this device | ||
510 | - interrupt-parent : the phandle for the interrupt controller | ||
511 | that services interrupts for this device. | ||
512 | |||
513 | Example Discovery Memory Controller node: | ||
514 | mem-ctrl@1400 { | ||
515 | compatible = "marvell,mv64360-mem-ctrl"; | ||
516 | reg = <0x1400 0x60>; | ||
517 | interrupts = <17>; | ||
518 | interrupt-parent = <&PIC>; | ||
519 | }; | ||
520 | |||
521 | |||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt new file mode 100644 index 000000000000..64bcb8be973c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | * Freescale Enhanced Secure Digital Host Controller (eSDHC) | ||
2 | |||
3 | The Enhanced Secure Digital Host Controller provides an interface | ||
4 | for MMC, SD, and SDIO types of memory cards. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : should be | ||
8 | "fsl,<chip>-esdhc", "fsl,esdhc" | ||
9 | - reg : should contain eSDHC registers location and length. | ||
10 | - interrupts : should contain eSDHC interrupt. | ||
11 | - interrupt-parent : interrupt source phandle. | ||
12 | - clock-frequency : specifies eSDHC base clock frequency. | ||
13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller | ||
14 | reports inverted write-protect state; | ||
15 | - sdhci,1-bit-only : (optional) specifies that a controller can | ||
16 | only handle 1-bit data transfers. | ||
17 | - sdhci,auto-cmd12: (optional) specifies that a controller can | ||
18 | only handle auto CMD12. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | sdhci@2e000 { | ||
23 | compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; | ||
24 | reg = <0x2e000 0x1000>; | ||
25 | interrupts = <42 0x8>; | ||
26 | interrupt-parent = <&ipic>; | ||
27 | /* Filled in by U-Boot */ | ||
28 | clock-frequency = <0>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt new file mode 100644 index 000000000000..c39ac2891951 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | MMC/SD/SDIO slot directly connected to a SPI bus | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "mmc-spi-slot". | ||
5 | - reg : should specify SPI address (chip-select number). | ||
6 | - spi-max-frequency : maximum frequency for this device (Hz). | ||
7 | - voltage-ranges : two cells are required, first cell specifies minimum | ||
8 | slot voltage (mV), second cell specifies maximum slot voltage (mV). | ||
9 | Several ranges could be specified. | ||
10 | - gpios : (optional) may specify GPIOs in this order: Card-Detect GPIO, | ||
11 | Write-Protect GPIO. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | mmc-slot@0 { | ||
16 | compatible = "fsl,mpc8323rdb-mmc-slot", | ||
17 | "mmc-spi-slot"; | ||
18 | reg = <0>; | ||
19 | gpios = <&qe_pio_d 14 1 | ||
20 | &qe_pio_d 15 0>; | ||
21 | voltage-ranges = <3300 3300>; | ||
22 | spi-max-frequency = <50000000>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt new file mode 100644 index 000000000000..a48b2cadc7f0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt | |||
@@ -0,0 +1,63 @@ | |||
1 | Freescale Localbus UPM programmed to work with NAND flash | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,upm-nand". | ||
5 | - reg : should specify localbus chip select and size used for the chip. | ||
6 | - fsl,upm-addr-offset : UPM pattern offset for the address latch. | ||
7 | - fsl,upm-cmd-offset : UPM pattern offset for the command latch. | ||
8 | |||
9 | Optional properties: | ||
10 | - fsl,upm-wait-flags : add chip-dependent short delays after running the | ||
11 | UPM pattern (0x1), after writing a data byte (0x2) or after | ||
12 | writing out a buffer (0x4). | ||
13 | - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. | ||
14 | The corresponding address lines are used to select the chip. | ||
15 | - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins | ||
16 | (R/B#). For multi-chip devices, "n" GPIO definitions are required | ||
17 | according to the number of chips. | ||
18 | - chip-delay : chip dependent delay for transfering data from array to | ||
19 | read registers (tR). Required if property "gpios" is not used | ||
20 | (R/B# pins not connected). | ||
21 | |||
22 | Examples: | ||
23 | |||
24 | upm@1,0 { | ||
25 | compatible = "fsl,upm-nand"; | ||
26 | reg = <1 0 1>; | ||
27 | fsl,upm-addr-offset = <16>; | ||
28 | fsl,upm-cmd-offset = <8>; | ||
29 | gpios = <&qe_pio_e 18 0>; | ||
30 | |||
31 | flash { | ||
32 | #address-cells = <1>; | ||
33 | #size-cells = <1>; | ||
34 | compatible = "..."; | ||
35 | |||
36 | partition@0 { | ||
37 | ... | ||
38 | }; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | upm@3,0 { | ||
43 | #address-cells = <0>; | ||
44 | #size-cells = <0>; | ||
45 | compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; | ||
46 | reg = <3 0x0 0x800>; | ||
47 | fsl,upm-addr-offset = <0x10>; | ||
48 | fsl,upm-cmd-offset = <0x08>; | ||
49 | /* Multi-chip NAND device */ | ||
50 | fsl,upm-addr-line-cs-offsets = <0x0 0x200>; | ||
51 | fsl,upm-wait-flags = <0x5>; | ||
52 | chip-delay = <25>; // in micro-seconds | ||
53 | |||
54 | nand@0 { | ||
55 | #address-cells = <1>; | ||
56 | #size-cells = <1>; | ||
57 | |||
58 | partition@0 { | ||
59 | label = "fs"; | ||
60 | reg = <0x00000000 0x10000000>; | ||
61 | }; | ||
62 | }; | ||
63 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt new file mode 100644 index 000000000000..80152cb567d9 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt | |||
@@ -0,0 +1,90 @@ | |||
1 | CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) | ||
2 | |||
3 | Flash chips (Memory Technology Devices) are often used for solid state | ||
4 | file systems on embedded devices. | ||
5 | |||
6 | - compatible : should contain the specific model of mtd chip(s) | ||
7 | used, if known, followed by either "cfi-flash", "jedec-flash" | ||
8 | or "mtd-ram". | ||
9 | - reg : Address range(s) of the mtd chip(s) | ||
10 | It's possible to (optionally) define multiple "reg" tuples so that | ||
11 | non-identical chips can be described in one node. | ||
12 | - bank-width : Width (in bytes) of the bank. Equal to the | ||
13 | device width times the number of interleaved chips. | ||
14 | - device-width : (optional) Width of a single mtd chip. If | ||
15 | omitted, assumed to be equal to 'bank-width'. | ||
16 | - #address-cells, #size-cells : Must be present if the device has | ||
17 | sub-nodes representing partitions (see below). In this case | ||
18 | both #address-cells and #size-cells must be equal to 1. | ||
19 | |||
20 | For JEDEC compatible devices, the following additional properties | ||
21 | are defined: | ||
22 | |||
23 | - vendor-id : Contains the flash chip's vendor id (1 byte). | ||
24 | - device-id : Contains the flash chip's device id (1 byte). | ||
25 | |||
26 | In addition to the information on the mtd bank itself, the | ||
27 | device tree may optionally contain additional information | ||
28 | describing partitions of the address space. This can be | ||
29 | used on platforms which have strong conventions about which | ||
30 | portions of a flash are used for what purposes, but which don't | ||
31 | use an on-flash partition table such as RedBoot. | ||
32 | |||
33 | Each partition is represented as a sub-node of the mtd device. | ||
34 | Each node's name represents the name of the corresponding | ||
35 | partition of the mtd device. | ||
36 | |||
37 | Flash partitions | ||
38 | - reg : The partition's offset and size within the mtd bank. | ||
39 | - label : (optional) The label / name for this partition. | ||
40 | If omitted, the label is taken from the node name (excluding | ||
41 | the unit address). | ||
42 | - read-only : (optional) This parameter, if present, is a hint to | ||
43 | Linux that this partition should only be mounted | ||
44 | read-only. This is usually used for flash partitions | ||
45 | containing early-boot firmware images or data which should not | ||
46 | be clobbered. | ||
47 | |||
48 | Example: | ||
49 | |||
50 | flash@ff000000 { | ||
51 | compatible = "amd,am29lv128ml", "cfi-flash"; | ||
52 | reg = <ff000000 01000000>; | ||
53 | bank-width = <4>; | ||
54 | device-width = <1>; | ||
55 | #address-cells = <1>; | ||
56 | #size-cells = <1>; | ||
57 | fs@0 { | ||
58 | label = "fs"; | ||
59 | reg = <0 f80000>; | ||
60 | }; | ||
61 | firmware@f80000 { | ||
62 | label ="firmware"; | ||
63 | reg = <f80000 80000>; | ||
64 | read-only; | ||
65 | }; | ||
66 | }; | ||
67 | |||
68 | Here an example with multiple "reg" tuples: | ||
69 | |||
70 | flash@f0000000,0 { | ||
71 | #address-cells = <1>; | ||
72 | #size-cells = <1>; | ||
73 | compatible = "intel,PC48F4400P0VB", "cfi-flash"; | ||
74 | reg = <0 0x00000000 0x02000000 | ||
75 | 0 0x02000000 0x02000000>; | ||
76 | bank-width = <2>; | ||
77 | partition@0 { | ||
78 | label = "test-part1"; | ||
79 | reg = <0 0x04000000>; | ||
80 | }; | ||
81 | }; | ||
82 | |||
83 | An example using SRAM: | ||
84 | |||
85 | sram@2,0 { | ||
86 | compatible = "samsung,k6f1616u6a", "mtd-ram"; | ||
87 | reg = <2 0 0x00200000>; | ||
88 | bank-width = <2>; | ||
89 | }; | ||
90 | |||
diff --git a/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt b/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt new file mode 100644 index 000000000000..2fa4fcd38fd6 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt | |||
@@ -0,0 +1,53 @@ | |||
1 | CAN Device Tree Bindings | ||
2 | ------------------------ | ||
3 | |||
4 | (c) 2006-2009 Secret Lab Technologies Ltd | ||
5 | Grant Likely <grant.likely@secretlab.ca> | ||
6 | |||
7 | fsl,mpc5200-mscan nodes | ||
8 | ----------------------- | ||
9 | In addition to the required compatible-, reg- and interrupt-properties, you can | ||
10 | also specify which clock source shall be used for the controller: | ||
11 | |||
12 | - fsl,mscan-clock-source : a string describing the clock source. Valid values | ||
13 | are: "ip" for ip bus clock | ||
14 | "ref" for reference clock (XTAL) | ||
15 | "ref" is default in case this property is not | ||
16 | present. | ||
17 | |||
18 | fsl,mpc5121-mscan nodes | ||
19 | ----------------------- | ||
20 | In addition to the required compatible-, reg- and interrupt-properties, you can | ||
21 | also specify which clock source and divider shall be used for the controller: | ||
22 | |||
23 | - fsl,mscan-clock-source : a string describing the clock source. Valid values | ||
24 | are: "ip" for ip bus clock | ||
25 | "ref" for reference clock | ||
26 | "sys" for system clock | ||
27 | If this property is not present, an optimal CAN | ||
28 | clock source and frequency based on the system | ||
29 | clock will be selected. If this is not possible, | ||
30 | the reference clock will be used. | ||
31 | |||
32 | - fsl,mscan-clock-divider: for the reference and system clock, an additional | ||
33 | clock divider can be specified. By default, a | ||
34 | value of 1 is used. | ||
35 | |||
36 | Note that the MPC5121 Rev. 1 processor is not supported. | ||
37 | |||
38 | Examples: | ||
39 | can@1300 { | ||
40 | compatible = "fsl,mpc5121-mscan"; | ||
41 | interrupts = <12 0x8>; | ||
42 | interrupt-parent = <&ipic>; | ||
43 | reg = <0x1300 0x80>; | ||
44 | }; | ||
45 | |||
46 | can@1380 { | ||
47 | compatible = "fsl,mpc5121-mscan"; | ||
48 | interrupts = <13 0x8>; | ||
49 | interrupt-parent = <&ipic>; | ||
50 | reg = <0x1380 0x80>; | ||
51 | fsl,mscan-clock-source = "ref"; | ||
52 | fsl,mscan-clock-divider = <3>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt new file mode 100644 index 000000000000..d6d209ded937 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/sja1000.txt | |||
@@ -0,0 +1,53 @@ | |||
1 | Memory mapped SJA1000 CAN controller from NXP (formerly Philips) | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "nxp,sja1000". | ||
6 | |||
7 | - reg : should specify the chip select, address offset and size required | ||
8 | to map the registers of the SJA1000. The size is usually 0x80. | ||
9 | |||
10 | - interrupts: property with a value describing the interrupt source | ||
11 | (number and sensitivity) required for the SJA1000. | ||
12 | |||
13 | Optional properties: | ||
14 | |||
15 | - nxp,external-clock-frequency : Frequency of the external oscillator | ||
16 | clock in Hz. Note that the internal clock frequency used by the | ||
17 | SJA1000 is half of that value. If not specified, a default value | ||
18 | of 16000000 (16 MHz) is used. | ||
19 | |||
20 | - nxp,tx-output-mode : operation mode of the TX output control logic: | ||
21 | <0x0> : bi-phase output mode | ||
22 | <0x1> : normal output mode (default) | ||
23 | <0x2> : test output mode | ||
24 | <0x3> : clock output mode | ||
25 | |||
26 | - nxp,tx-output-config : TX output pin configuration: | ||
27 | <0x01> : TX0 invert | ||
28 | <0x02> : TX0 pull-down (default) | ||
29 | <0x04> : TX0 pull-up | ||
30 | <0x06> : TX0 push-pull | ||
31 | <0x08> : TX1 invert | ||
32 | <0x10> : TX1 pull-down | ||
33 | <0x20> : TX1 pull-up | ||
34 | <0x30> : TX1 push-pull | ||
35 | |||
36 | - nxp,clock-out-frequency : clock frequency in Hz on the CLKOUT pin. | ||
37 | If not specified or if the specified value is 0, the CLKOUT pin | ||
38 | will be disabled. | ||
39 | |||
40 | - nxp,no-comparator-bypass : Allows to disable the CAN input comperator. | ||
41 | |||
42 | For futher information, please have a look to the SJA1000 data sheet. | ||
43 | |||
44 | Examples: | ||
45 | |||
46 | can@3,100 { | ||
47 | compatible = "nxp,sja1000"; | ||
48 | reg = <3 0x100 0x80>; | ||
49 | interrupts = <2 0>; | ||
50 | interrupt-parent = <&mpic>; | ||
51 | nxp,external-clock-frequency = <16000000>; | ||
52 | }; | ||
53 | |||
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt new file mode 100644 index 000000000000..edb7ae19e868 --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | |||
@@ -0,0 +1,76 @@ | |||
1 | * MDIO IO device | ||
2 | |||
3 | The MDIO is a bus to which the PHY devices are connected. For each | ||
4 | device that exists on this bus, a child node should be created. See | ||
5 | the definition of the PHY node in booting-without-of.txt for an example | ||
6 | of how to define a PHY. | ||
7 | |||
8 | Required properties: | ||
9 | - reg : Offset and length of the register set for the device | ||
10 | - compatible : Should define the compatible device type for the | ||
11 | mdio. Currently, this is most likely to be "fsl,gianfar-mdio" | ||
12 | |||
13 | Example: | ||
14 | |||
15 | mdio@24520 { | ||
16 | reg = <24520 20>; | ||
17 | compatible = "fsl,gianfar-mdio"; | ||
18 | |||
19 | ethernet-phy@0 { | ||
20 | ...... | ||
21 | }; | ||
22 | }; | ||
23 | |||
24 | * TBI Internal MDIO bus | ||
25 | |||
26 | As of this writing, every tsec is associated with an internal TBI PHY. | ||
27 | This PHY is accessed through the local MDIO bus. These buses are defined | ||
28 | similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". | ||
29 | The TBI PHYs underneath them are similar to normal PHYs, but the reg property | ||
30 | is considered instructive, rather than descriptive. The reg property should | ||
31 | be chosen so it doesn't interfere with other PHYs on the bus. | ||
32 | |||
33 | * Gianfar-compatible ethernet nodes | ||
34 | |||
35 | Properties: | ||
36 | |||
37 | - device_type : Should be "network" | ||
38 | - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" | ||
39 | - compatible : Should be "gianfar" | ||
40 | - reg : Offset and length of the register set for the device | ||
41 | - local-mac-address : List of bytes representing the ethernet address of | ||
42 | this controller | ||
43 | - interrupts : For FEC devices, the first interrupt is the device's | ||
44 | interrupt. For TSEC and eTSEC devices, the first interrupt is | ||
45 | transmit, the second is receive, and the third is error. | ||
46 | - phy-handle : The phandle for the PHY connected to this ethernet | ||
47 | controller. | ||
48 | - fixed-link : <a b c d e> where a is emulated phy id - choose any, | ||
49 | but unique to the all specified fixed-links, b is duplex - 0 half, | ||
50 | 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no | ||
51 | pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause. | ||
52 | - phy-connection-type : a string naming the controller/PHY interface type, | ||
53 | i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii", | ||
54 | "tbi", or "rtbi". This property is only really needed if the connection | ||
55 | is of type "rgmii-id", as all other connection types are detected by | ||
56 | hardware. | ||
57 | - fsl,magic-packet : If present, indicates that the hardware supports | ||
58 | waking up via magic packet. | ||
59 | - bd-stash : If present, indicates that the hardware supports stashing | ||
60 | buffer descriptors in the L2. | ||
61 | - rx-stash-len : Denotes the number of bytes of a received buffer to stash | ||
62 | in the L2. | ||
63 | - rx-stash-idx : Denotes the index of the first byte from the received | ||
64 | buffer to stash in the L2. | ||
65 | |||
66 | Example: | ||
67 | ethernet@24000 { | ||
68 | device_type = "network"; | ||
69 | model = "TSEC"; | ||
70 | compatible = "gianfar"; | ||
71 | reg = <0x24000 0x1000>; | ||
72 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | ||
73 | interrupts = <29 2 30 2 34 2>; | ||
74 | interrupt-parent = <&mpic>; | ||
75 | phy-handle = <&phy0> | ||
76 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt new file mode 100644 index 000000000000..bc9549529014 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-gpio.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | MDIO on GPIOs | ||
2 | |||
3 | Currently defined compatibles: | ||
4 | - virtual,gpio-mdio | ||
5 | |||
6 | MDC and MDIO lines connected to GPIO controllers are listed in the | ||
7 | gpios property as described in section VIII.1 in the following order: | ||
8 | |||
9 | MDC, MDIO. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | mdio { | ||
14 | compatible = "virtual,mdio-gpio"; | ||
15 | #address-cells = <1>; | ||
16 | #size-cells = <0>; | ||
17 | gpios = <&qe_pio_a 11 | ||
18 | &qe_pio_c 6>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt new file mode 100644 index 000000000000..bb8c742eb8c5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/phy.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | PHY nodes | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - device_type : Should be "ethernet-phy" | ||
6 | - interrupts : <a b> where a is the interrupt number and b is a | ||
7 | field that represents an encoding of the sense and level | ||
8 | information for the interrupt. This should be encoded based on | ||
9 | the information in section 2) depending on the type of interrupt | ||
10 | controller you have. | ||
11 | - interrupt-parent : the phandle for the interrupt controller that | ||
12 | services interrupts for this device. | ||
13 | - reg : The ID number for the phy, usually a small integer | ||
14 | - linux,phandle : phandle for this node; likely referenced by an | ||
15 | ethernet controller node. | ||
16 | |||
17 | Example: | ||
18 | |||
19 | ethernet-phy@0 { | ||
20 | linux,phandle = <2452000> | ||
21 | interrupt-parent = <40000>; | ||
22 | interrupts = <35 1>; | ||
23 | reg = <0>; | ||
24 | device_type = "ethernet-phy"; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt b/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt new file mode 100644 index 000000000000..35a465362408 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt | |||
@@ -0,0 +1,40 @@ | |||
1 | * Freescale 83xx and 512x PCI bridges | ||
2 | |||
3 | Freescale 83xx and 512x SOCs include the same pci bridge core. | ||
4 | |||
5 | 83xx/512x specific notes: | ||
6 | - reg: should contain two address length tuples | ||
7 | The first is for the internal pci bridge registers | ||
8 | The second is for the pci config space access registers | ||
9 | |||
10 | Example (MPC8313ERDB) | ||
11 | pci0: pci@e0008500 { | ||
12 | cell-index = <1>; | ||
13 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
14 | interrupt-map = < | ||
15 | /* IDSEL 0x0E -mini PCI */ | ||
16 | 0x7000 0x0 0x0 0x1 &ipic 18 0x8 | ||
17 | 0x7000 0x0 0x0 0x2 &ipic 18 0x8 | ||
18 | 0x7000 0x0 0x0 0x3 &ipic 18 0x8 | ||
19 | 0x7000 0x0 0x0 0x4 &ipic 18 0x8 | ||
20 | |||
21 | /* IDSEL 0x0F - PCI slot */ | ||
22 | 0x7800 0x0 0x0 0x1 &ipic 17 0x8 | ||
23 | 0x7800 0x0 0x0 0x2 &ipic 18 0x8 | ||
24 | 0x7800 0x0 0x0 0x3 &ipic 17 0x8 | ||
25 | 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; | ||
26 | interrupt-parent = <&ipic>; | ||
27 | interrupts = <66 0x8>; | ||
28 | bus-range = <0x0 0x0>; | ||
29 | ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 | ||
30 | 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | ||
31 | 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; | ||
32 | clock-frequency = <66666666>; | ||
33 | #interrupt-cells = <1>; | ||
34 | #size-cells = <2>; | ||
35 | #address-cells = <3>; | ||
36 | reg = <0xe0008500 0x100 /* internal registers */ | ||
37 | 0xe0008300 0x8>; /* config space access registers */ | ||
38 | compatible = "fsl,mpc8349-pci"; | ||
39 | device_type = "pci"; | ||
40 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt b/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt new file mode 100644 index 000000000000..ee459806d35e --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt | |||
@@ -0,0 +1,52 @@ | |||
1 | PPC4xx Clock Power Management (CPM) node | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : compatible list, currently only "ibm,cpm" | ||
5 | - dcr-access-method : "native" | ||
6 | - dcr-reg : < DCR register range > | ||
7 | |||
8 | Optional properties: | ||
9 | - er-offset : All 4xx SoCs with a CPM controller have | ||
10 | one of two different order for the CPM | ||
11 | registers. Some have the CPM registers | ||
12 | in the following order (ER,FR,SR). The | ||
13 | others have them in the following order | ||
14 | (SR,ER,FR). For the second case set | ||
15 | er-offset = <1>. | ||
16 | - unused-units : specifier consist of one cell. For each | ||
17 | bit in the cell, the corresponding bit | ||
18 | in CPM will be set to turn off unused | ||
19 | devices. | ||
20 | - idle-doze : specifier consist of one cell. For each | ||
21 | bit in the cell, the corresponding bit | ||
22 | in CPM will be set to turn off unused | ||
23 | devices. This is usually just CPM[CPU]. | ||
24 | - standby : specifier consist of one cell. For each | ||
25 | bit in the cell, the corresponding bit | ||
26 | in CPM will be set on standby and | ||
27 | restored on resume. | ||
28 | - suspend : specifier consist of one cell. For each | ||
29 | bit in the cell, the corresponding bit | ||
30 | in CPM will be set on suspend (mem) and | ||
31 | restored on resume. Note, for standby | ||
32 | and suspend the corresponding bits can | ||
33 | be different or the same. Usually for | ||
34 | standby only class 2 and 3 units are set. | ||
35 | However, the interface does not care. | ||
36 | If they are the same, the additional | ||
37 | power saving will be seeing if support | ||
38 | is available to put the DDR in self | ||
39 | refresh mode and any additional power | ||
40 | saving techniques for the specific SoC. | ||
41 | |||
42 | Example: | ||
43 | CPM0: cpm { | ||
44 | compatible = "ibm,cpm"; | ||
45 | dcr-access-method = "native"; | ||
46 | dcr-reg = <0x160 0x003>; | ||
47 | er-offset = <0>; | ||
48 | unused-units = <0x00000100>; | ||
49 | idle-doze = <0x02000000>; | ||
50 | standby = <0xfeff0000>; | ||
51 | suspend = <0xfeff791d>; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt new file mode 100644 index 000000000000..2161334a7ca5 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt | |||
@@ -0,0 +1,148 @@ | |||
1 | 4xx/Axon EMAC ethernet nodes | ||
2 | |||
3 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | ||
4 | the Axon bridge. To operate this needs to interact with a ths | ||
5 | special McMAL DMA controller, and sometimes an RGMII or ZMII | ||
6 | interface. In addition to the nodes and properties described | ||
7 | below, the node for the OPB bus on which the EMAC sits must have a | ||
8 | correct clock-frequency property. | ||
9 | |||
10 | i) The EMAC node itself | ||
11 | |||
12 | Required properties: | ||
13 | - device_type : "network" | ||
14 | |||
15 | - compatible : compatible list, contains 2 entries, first is | ||
16 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | ||
17 | 405gp, Axon) and second is either "ibm,emac" or | ||
18 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | ||
19 | "ibm,emac4" | ||
20 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | ||
21 | - interrupt-parent : optional, if needed for interrupt mapping | ||
22 | - reg : <registers mapping> | ||
23 | - local-mac-address : 6 bytes, MAC address | ||
24 | - mal-device : phandle of the associated McMAL node | ||
25 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | ||
26 | with this EMAC | ||
27 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | ||
28 | with this EMAC | ||
29 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | ||
30 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | ||
31 | each Axon chip) | ||
32 | - max-frame-size : 1 cell, maximum frame size supported in bytes | ||
33 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | ||
34 | operations. | ||
35 | For Axon, 2048 | ||
36 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | ||
37 | operations. | ||
38 | For Axon, 2048. | ||
39 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | ||
40 | thresholds). | ||
41 | For Axon, 0x00000010 | ||
42 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | ||
43 | in bytes. | ||
44 | For Axon, 0x00000100 (I think ...) | ||
45 | - phy-mode : string, mode of operations of the PHY interface. | ||
46 | Supported values are: "mii", "rmii", "smii", "rgmii", | ||
47 | "tbi", "gmii", rtbi", "sgmii". | ||
48 | For Axon on CAB, it is "rgmii" | ||
49 | - mdio-device : 1 cell, required iff using shared MDIO registers | ||
50 | (440EP). phandle of the EMAC to use to drive the | ||
51 | MDIO lines for the PHY used by this EMAC. | ||
52 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | ||
53 | the ZMII device node | ||
54 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | ||
55 | channel or 0xffffffff if ZMII is only used for MDIO. | ||
56 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | ||
57 | of the RGMII device node. | ||
58 | For Axon: phandle of plb5/plb4/opb/rgmii | ||
59 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | ||
60 | RGMII channel is used by this EMAC. | ||
61 | Fox Axon: present, whatever value is appropriate for each | ||
62 | EMAC, that is the content of the current (bogus) "phy-port" | ||
63 | property. | ||
64 | |||
65 | Optional properties: | ||
66 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | ||
67 | a search is performed. | ||
68 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | ||
69 | for, used if phy-address is absent. bit 0x00000001 is | ||
70 | MDIO address 0. | ||
71 | For Axon it can be absent, though my current driver | ||
72 | doesn't handle phy-address yet so for now, keep | ||
73 | 0x00ffffff in it. | ||
74 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec | ||
75 | operations (if absent the value is the same as | ||
76 | rx-fifo-size). For Axon, either absent or 2048. | ||
77 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | ||
78 | operations (if absent the value is the same as | ||
79 | tx-fifo-size). For Axon, either absent or 2048. | ||
80 | - tah-device : 1 cell, optional. If connected to a TAH engine for | ||
81 | offload, phandle of the TAH device node. | ||
82 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | ||
83 | TAH engine. | ||
84 | |||
85 | Example: | ||
86 | |||
87 | EMAC0: ethernet@40000800 { | ||
88 | device_type = "network"; | ||
89 | compatible = "ibm,emac-440gp", "ibm,emac"; | ||
90 | interrupt-parent = <&UIC1>; | ||
91 | interrupts = <1c 4 1d 4>; | ||
92 | reg = <40000800 70>; | ||
93 | local-mac-address = [00 04 AC E3 1B 1E]; | ||
94 | mal-device = <&MAL0>; | ||
95 | mal-tx-channel = <0 1>; | ||
96 | mal-rx-channel = <0>; | ||
97 | cell-index = <0>; | ||
98 | max-frame-size = <5dc>; | ||
99 | rx-fifo-size = <1000>; | ||
100 | tx-fifo-size = <800>; | ||
101 | phy-mode = "rmii"; | ||
102 | phy-map = <00000001>; | ||
103 | zmii-device = <&ZMII0>; | ||
104 | zmii-channel = <0>; | ||
105 | }; | ||
106 | |||
107 | ii) McMAL node | ||
108 | |||
109 | Required properties: | ||
110 | - device_type : "dma-controller" | ||
111 | - compatible : compatible list, containing 2 entries, first is | ||
112 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | ||
113 | emac) and the second is either "ibm,mcmal" or | ||
114 | "ibm,mcmal2". | ||
115 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | ||
116 | - interrupts : <interrupt mapping for the MAL interrupts sources: | ||
117 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | ||
118 | For Axon: This is _different_ from the current | ||
119 | firmware. We use the "delayed" interrupts for txeob | ||
120 | and rxeob. Thus we end up with mapping those 5 MPIC | ||
121 | interrupts, all level positive sensitive: 10, 11, 32, | ||
122 | 33, 34 (in decimal) | ||
123 | - dcr-reg : < DCR registers range > | ||
124 | - dcr-parent : if needed for dcr-reg | ||
125 | - num-tx-chans : 1 cell, number of Tx channels | ||
126 | - num-rx-chans : 1 cell, number of Rx channels | ||
127 | |||
128 | iii) ZMII node | ||
129 | |||
130 | Required properties: | ||
131 | - compatible : compatible list, containing 2 entries, first is | ||
132 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | ||
133 | EMAC) and the second is "ibm,zmii". | ||
134 | For Axon, there is no ZMII node. | ||
135 | - reg : <registers mapping> | ||
136 | |||
137 | iv) RGMII node | ||
138 | |||
139 | Required properties: | ||
140 | - compatible : compatible list, containing 2 entries, first is | ||
141 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | ||
142 | EMAC) and the second is "ibm,rgmii". | ||
143 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | ||
144 | - reg : <registers mapping> | ||
145 | - revision : as provided by the RGMII new version register if | ||
146 | available. | ||
147 | For Axon: 0x0000012a | ||
148 | |||
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt b/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt new file mode 100644 index 000000000000..869f0b5f16e8 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | AMCC NDFC (NanD Flash Controller) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "ibm,ndfc". | ||
5 | - reg : should specify chip select and size used for the chip (0x2000). | ||
6 | |||
7 | Optional properties: | ||
8 | - ccr : NDFC config and control register value (default 0). | ||
9 | - bank-settings : NDFC bank configuration register value (default 0). | ||
10 | |||
11 | Notes: | ||
12 | - partition(s) - follows the OF MTD standard for partitions | ||
13 | |||
14 | Example: | ||
15 | |||
16 | ndfc@1,0 { | ||
17 | compatible = "ibm,ndfc"; | ||
18 | reg = <0x00000001 0x00000000 0x00002000>; | ||
19 | ccr = <0x00001000>; | ||
20 | bank-settings = <0x80002222>; | ||
21 | #address-cells = <1>; | ||
22 | #size-cells = <1>; | ||
23 | |||
24 | nand { | ||
25 | #address-cells = <1>; | ||
26 | #size-cells = <1>; | ||
27 | |||
28 | partition@0 { | ||
29 | label = "kernel"; | ||
30 | reg = <0x00000000 0x00200000>; | ||
31 | }; | ||
32 | partition@200000 { | ||
33 | label = "root"; | ||
34 | reg = <0x00200000 0x03E00000>; | ||
35 | }; | ||
36 | }; | ||
37 | }; | ||
38 | |||
39 | |||
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt b/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt new file mode 100644 index 000000000000..515ebcf1b97d --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt | |||
@@ -0,0 +1,93 @@ | |||
1 | PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) | ||
2 | |||
3 | Device nodes needed for operation of the ppc440spe-adma driver | ||
4 | are specified hereby. These are I2O/DMA, DMA and XOR nodes | ||
5 | for DMA engines and Memory Queue Module node. The latter is used | ||
6 | by ADMA driver for configuration of RAID-6 H/W capabilities of | ||
7 | the PPC440SPe. In addition to the nodes and properties described | ||
8 | below, the ranges property of PLB node must specify ranges for | ||
9 | DMA devices. | ||
10 | |||
11 | i) The I2O node | ||
12 | |||
13 | Required properties: | ||
14 | |||
15 | - compatible : "ibm,i2o-440spe"; | ||
16 | - reg : <registers mapping> | ||
17 | - dcr-reg : <DCR registers range> | ||
18 | |||
19 | Example: | ||
20 | |||
21 | I2O: i2o@400100000 { | ||
22 | compatible = "ibm,i2o-440spe"; | ||
23 | reg = <0x00000004 0x00100000 0x100>; | ||
24 | dcr-reg = <0x060 0x020>; | ||
25 | }; | ||
26 | |||
27 | |||
28 | ii) The DMA node | ||
29 | |||
30 | Required properties: | ||
31 | |||
32 | - compatible : "ibm,dma-440spe"; | ||
33 | - cell-index : 1 cell, hardware index of the DMA engine | ||
34 | (typically 0x0 and 0x1 for DMA0 and DMA1) | ||
35 | - reg : <registers mapping> | ||
36 | - dcr-reg : <DCR registers range> | ||
37 | - interrupts : <interrupt mapping for DMA0/1 interrupts sources: | ||
38 | 2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0) | ||
39 | and DMA Error IRQ (on UIC1). The latter is common | ||
40 | for both DMA engines>. | ||
41 | - interrupt-parent : needed for interrupt mapping | ||
42 | |||
43 | Example: | ||
44 | |||
45 | DMA0: dma0@400100100 { | ||
46 | compatible = "ibm,dma-440spe"; | ||
47 | cell-index = <0>; | ||
48 | reg = <0x00000004 0x00100100 0x100>; | ||
49 | dcr-reg = <0x060 0x020>; | ||
50 | interrupt-parent = <&DMA0>; | ||
51 | interrupts = <0 1>; | ||
52 | #interrupt-cells = <1>; | ||
53 | #address-cells = <0>; | ||
54 | #size-cells = <0>; | ||
55 | interrupt-map = < | ||
56 | 0 &UIC0 0x14 4 | ||
57 | 1 &UIC1 0x16 4>; | ||
58 | }; | ||
59 | |||
60 | |||
61 | iii) XOR Accelerator node | ||
62 | |||
63 | Required properties: | ||
64 | |||
65 | - compatible : "amcc,xor-accelerator"; | ||
66 | - reg : <registers mapping> | ||
67 | - interrupts : <interrupt mapping for XOR interrupt source> | ||
68 | - interrupt-parent : for interrupt mapping | ||
69 | |||
70 | Example: | ||
71 | |||
72 | xor-accel@400200000 { | ||
73 | compatible = "amcc,xor-accelerator"; | ||
74 | reg = <0x00000004 0x00200000 0x400>; | ||
75 | interrupt-parent = <&UIC1>; | ||
76 | interrupts = <0x1f 4>; | ||
77 | }; | ||
78 | |||
79 | |||
80 | iv) Memory Queue Module node | ||
81 | |||
82 | Required properties: | ||
83 | |||
84 | - compatible : "ibm,mq-440spe"; | ||
85 | - dcr-reg : <DCR registers range> | ||
86 | |||
87 | Example: | ||
88 | |||
89 | MQ0: mq { | ||
90 | compatible = "ibm,mq-440spe"; | ||
91 | dcr-reg = <0x040 0x020>; | ||
92 | }; | ||
93 | |||
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt b/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt new file mode 100644 index 000000000000..d7217260589c --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | Reboot property to control system reboot on PPC4xx systems: | ||
2 | |||
3 | By setting "reset_type" to one of the following values, the default | ||
4 | software reset mechanism may be overidden. Here the possible values of | ||
5 | "reset_type": | ||
6 | |||
7 | 1 - PPC4xx core reset | ||
8 | 2 - PPC4xx chip reset | ||
9 | 3 - PPC4xx system reset (default) | ||
10 | |||
11 | Example: | ||
12 | |||
13 | cpu@0 { | ||
14 | device_type = "cpu"; | ||
15 | model = "PowerPC,440SPe"; | ||
16 | ... | ||
17 | reset-type = <2>; /* Use chip-reset */ | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt new file mode 100644 index 000000000000..39e941515a36 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt | |||
@@ -0,0 +1,63 @@ | |||
1 | * Board Control and Status (BCSR) | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : Should be "fsl,<board>-bcsr" | ||
6 | - reg : Offset and length of the register set for the device | ||
7 | |||
8 | Example: | ||
9 | |||
10 | bcsr@f8000000 { | ||
11 | compatible = "fsl,mpc8360mds-bcsr"; | ||
12 | reg = <f8000000 8000>; | ||
13 | }; | ||
14 | |||
15 | * Freescale on board FPGA | ||
16 | |||
17 | This is the memory-mapped registers for on board FPGA. | ||
18 | |||
19 | Required properities: | ||
20 | - compatible : should be "fsl,fpga-pixis". | ||
21 | - reg : should contain the address and the length of the FPPGA register | ||
22 | set. | ||
23 | - interrupt-parent: should specify phandle for the interrupt controller. | ||
24 | - interrupts : should specify event (wakeup) IRQ. | ||
25 | |||
26 | Example (MPC8610HPCD): | ||
27 | |||
28 | board-control@e8000000 { | ||
29 | compatible = "fsl,fpga-pixis"; | ||
30 | reg = <0xe8000000 32>; | ||
31 | interrupt-parent = <&mpic>; | ||
32 | interrupts = <8 8>; | ||
33 | }; | ||
34 | |||
35 | * Freescale BCSR GPIO banks | ||
36 | |||
37 | Some BCSR registers act as simple GPIO controllers, each such | ||
38 | register can be represented by the gpio-controller node. | ||
39 | |||
40 | Required properities: | ||
41 | - compatible : Should be "fsl,<board>-bcsr-gpio". | ||
42 | - reg : Should contain the address and the length of the GPIO bank | ||
43 | register. | ||
44 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
45 | second cell is used to specify optional parameters (currently unused). | ||
46 | - gpio-controller : Marks the port as GPIO controller. | ||
47 | |||
48 | Example: | ||
49 | |||
50 | bcsr@1,0 { | ||
51 | #address-cells = <1>; | ||
52 | #size-cells = <1>; | ||
53 | compatible = "fsl,mpc8360mds-bcsr"; | ||
54 | reg = <1 0 0x8000>; | ||
55 | ranges = <0 1 0 0x8000>; | ||
56 | |||
57 | bcsr13: gpio-controller@d { | ||
58 | #gpio-cells = <2>; | ||
59 | compatible = "fsl,mpc8360mds-bcsr-gpio"; | ||
60 | reg = <0xd 1>; | ||
61 | gpio-controller; | ||
62 | }; | ||
63 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt new file mode 100644 index 000000000000..160c752484b4 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt | |||
@@ -0,0 +1,67 @@ | |||
1 | * Freescale Communications Processor Module | ||
2 | |||
3 | NOTE: This is an interim binding, and will likely change slightly, | ||
4 | as more devices are supported. The QE bindings especially are | ||
5 | incomplete. | ||
6 | |||
7 | * Root CPM node | ||
8 | |||
9 | Properties: | ||
10 | - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe". | ||
11 | - reg : A 48-byte region beginning with CPCR. | ||
12 | |||
13 | Example: | ||
14 | cpm@119c0 { | ||
15 | #address-cells = <1>; | ||
16 | #size-cells = <1>; | ||
17 | #interrupt-cells = <2>; | ||
18 | compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; | ||
19 | reg = <119c0 30>; | ||
20 | } | ||
21 | |||
22 | * Properties common to multiple CPM/QE devices | ||
23 | |||
24 | - fsl,cpm-command : This value is ORed with the opcode and command flag | ||
25 | to specify the device on which a CPM command operates. | ||
26 | |||
27 | - fsl,cpm-brg : Indicates which baud rate generator the device | ||
28 | is associated with. If absent, an unused BRG | ||
29 | should be dynamically allocated. If zero, the | ||
30 | device uses an external clock rather than a BRG. | ||
31 | |||
32 | - reg : Unless otherwise specified, the first resource represents the | ||
33 | scc/fcc/ucc registers, and the second represents the device's | ||
34 | parameter RAM region (if it has one). | ||
35 | |||
36 | * Multi-User RAM (MURAM) | ||
37 | |||
38 | The multi-user/dual-ported RAM is expressed as a bus under the CPM node. | ||
39 | |||
40 | Ranges must be set up subject to the following restrictions: | ||
41 | |||
42 | - Children's reg nodes must be offsets from the start of all muram, even | ||
43 | if the user-data area does not begin at zero. | ||
44 | - If multiple range entries are used, the difference between the parent | ||
45 | address and the child address must be the same in all, so that a single | ||
46 | mapping can cover them all while maintaining the ability to determine | ||
47 | CPM-side offsets with pointer subtraction. It is recommended that | ||
48 | multiple range entries not be used. | ||
49 | - A child address of zero must be translatable, even if no reg resources | ||
50 | contain it. | ||
51 | |||
52 | A child "data" node must exist, compatible with "fsl,cpm-muram-data", to | ||
53 | indicate the portion of muram that is usable by the OS for arbitrary | ||
54 | purposes. The data node may have an arbitrary number of reg resources, | ||
55 | all of which contribute to the allocatable muram pool. | ||
56 | |||
57 | Example, based on mpc8272: | ||
58 | muram@0 { | ||
59 | #address-cells = <1>; | ||
60 | #size-cells = <1>; | ||
61 | ranges = <0 0 10000>; | ||
62 | |||
63 | data@0 { | ||
64 | compatible = "fsl,cpm-muram-data"; | ||
65 | reg = <0 2000 9800 800>; | ||
66 | }; | ||
67 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt new file mode 100644 index 000000000000..4c7d45eaf025 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Baud Rate Generators | ||
2 | |||
3 | Currently defined compatibles: | ||
4 | fsl,cpm-brg | ||
5 | fsl,cpm1-brg | ||
6 | fsl,cpm2-brg | ||
7 | |||
8 | Properties: | ||
9 | - reg : There may be an arbitrary number of reg resources; BRG | ||
10 | numbers are assigned to these in order. | ||
11 | - clock-frequency : Specifies the base frequency driving | ||
12 | the BRG. | ||
13 | |||
14 | Example: | ||
15 | brg@119f0 { | ||
16 | compatible = "fsl,mpc8272-brg", | ||
17 | "fsl,cpm2-brg", | ||
18 | "fsl,cpm-brg"; | ||
19 | reg = <119f0 10 115f0 10>; | ||
20 | clock-frequency = <d#25000000>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt new file mode 100644 index 000000000000..87bc6048667e --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt | |||
@@ -0,0 +1,41 @@ | |||
1 | * I2C | ||
2 | |||
3 | The I2C controller is expressed as a bus under the CPM node. | ||
4 | |||
5 | Properties: | ||
6 | - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c" | ||
7 | - reg : On CPM2 devices, the second resource doesn't specify the I2C | ||
8 | Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM | ||
9 | (typically 0x8afc 0x2). | ||
10 | - #address-cells : Should be one. The cell is the i2c device address with | ||
11 | the r/w bit set to zero. | ||
12 | - #size-cells : Should be zero. | ||
13 | - clock-frequency : Can be used to set the i2c clock frequency. If | ||
14 | unspecified, a default frequency of 60kHz is being used. | ||
15 | The following two properties are deprecated. They are only used by legacy | ||
16 | i2c drivers to find the bus to probe: | ||
17 | - linux,i2c-index : Can be used to hard code an i2c bus number. By default, | ||
18 | the bus number is dynamically assigned by the i2c core. | ||
19 | - linux,i2c-class : Can be used to override the i2c class. The class is used | ||
20 | by legacy i2c device drivers to find a bus in a specific context like | ||
21 | system management, video or sound. By default, I2C_CLASS_HWMON (1) is | ||
22 | being used. The definition of the classes can be found in | ||
23 | include/i2c/i2c.h | ||
24 | |||
25 | Example, based on mpc823: | ||
26 | |||
27 | i2c@860 { | ||
28 | compatible = "fsl,mpc823-i2c", | ||
29 | "fsl,cpm1-i2c"; | ||
30 | reg = <0x860 0x20 0x3c80 0x30>; | ||
31 | interrupts = <16>; | ||
32 | interrupt-parent = <&CPM_PIC>; | ||
33 | fsl,cpm-command = <0x10>; | ||
34 | #address-cells = <1>; | ||
35 | #size-cells = <0>; | ||
36 | |||
37 | rtc@68 { | ||
38 | compatible = "dallas,ds1307"; | ||
39 | reg = <0x68>; | ||
40 | }; | ||
41 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt new file mode 100644 index 000000000000..8e3ee1681618 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | * Interrupt Controllers | ||
2 | |||
3 | Currently defined compatibles: | ||
4 | - fsl,cpm1-pic | ||
5 | - only one interrupt cell | ||
6 | - fsl,pq1-pic | ||
7 | - fsl,cpm2-pic | ||
8 | - second interrupt cell is level/sense: | ||
9 | - 2 is falling edge | ||
10 | - 8 is active low | ||
11 | |||
12 | Example: | ||
13 | interrupt-controller@10c00 { | ||
14 | #interrupt-cells = <2>; | ||
15 | interrupt-controller; | ||
16 | reg = <10c00 80>; | ||
17 | compatible = "mpc8272-pic", "fsl,cpm2-pic"; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt new file mode 100644 index 000000000000..74bfda4bb824 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | * USB (Universal Serial Bus Controller) | ||
2 | |||
3 | Properties: | ||
4 | - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb" | ||
5 | |||
6 | Example: | ||
7 | usb@11bc0 { | ||
8 | #address-cells = <1>; | ||
9 | #size-cells = <0>; | ||
10 | compatible = "fsl,cpm2-usb"; | ||
11 | reg = <11b60 18 8b00 100>; | ||
12 | interrupts = <b 8>; | ||
13 | interrupt-parent = <&PIC>; | ||
14 | fsl,cpm-command = <2e600000>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt new file mode 100644 index 000000000000..349f79fd7076 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | Every GPIO controller node must have #gpio-cells property defined, | ||
2 | this information will be used to translate gpio-specifiers. | ||
3 | |||
4 | On CPM1 devices, all ports are using slightly different register layouts. | ||
5 | Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. | ||
6 | |||
7 | On CPM2 devices, all ports are 32bit ports and use a common register layout. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", | ||
11 | "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", | ||
12 | "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" | ||
13 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
14 | second cell is used to specify optional parameters (currently unused). | ||
15 | - gpio-controller : Marks the port as GPIO controller. | ||
16 | |||
17 | Example of three SOC GPIO banks defined as gpio-controller nodes: | ||
18 | |||
19 | CPM1_PIO_A: gpio-controller@950 { | ||
20 | #gpio-cells = <2>; | ||
21 | compatible = "fsl,cpm1-pario-bank-a"; | ||
22 | reg = <0x950 0x10>; | ||
23 | gpio-controller; | ||
24 | }; | ||
25 | |||
26 | CPM1_PIO_B: gpio-controller@ab8 { | ||
27 | #gpio-cells = <2>; | ||
28 | compatible = "fsl,cpm1-pario-bank-b"; | ||
29 | reg = <0xab8 0x10>; | ||
30 | gpio-controller; | ||
31 | }; | ||
32 | |||
33 | CPM1_PIO_E: gpio-controller@ac8 { | ||
34 | #gpio-cells = <2>; | ||
35 | compatible = "fsl,cpm1-pario-bank-e"; | ||
36 | reg = <0xac8 0x18>; | ||
37 | gpio-controller; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt new file mode 100644 index 000000000000..0e4269446580 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt | |||
@@ -0,0 +1,45 @@ | |||
1 | * Network | ||
2 | |||
3 | Currently defined compatibles: | ||
4 | - fsl,cpm1-scc-enet | ||
5 | - fsl,cpm2-scc-enet | ||
6 | - fsl,cpm1-fec-enet | ||
7 | - fsl,cpm2-fcc-enet (third resource is GFEMR) | ||
8 | - fsl,qe-enet | ||
9 | |||
10 | Example: | ||
11 | |||
12 | ethernet@11300 { | ||
13 | device_type = "network"; | ||
14 | compatible = "fsl,mpc8272-fcc-enet", | ||
15 | "fsl,cpm2-fcc-enet"; | ||
16 | reg = <11300 20 8400 100 11390 1>; | ||
17 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
18 | interrupts = <20 8>; | ||
19 | interrupt-parent = <&PIC>; | ||
20 | phy-handle = <&PHY0>; | ||
21 | fsl,cpm-command = <12000300>; | ||
22 | }; | ||
23 | |||
24 | * MDIO | ||
25 | |||
26 | Currently defined compatibles: | ||
27 | fsl,pq1-fec-mdio (reg is same as first resource of FEC device) | ||
28 | fsl,cpm2-mdio-bitbang (reg is port C registers) | ||
29 | |||
30 | Properties for fsl,cpm2-mdio-bitbang: | ||
31 | fsl,mdio-pin : pin of port C controlling mdio data | ||
32 | fsl,mdc-pin : pin of port C controlling mdio clock | ||
33 | |||
34 | Example: | ||
35 | mdio@10d40 { | ||
36 | device_type = "mdio"; | ||
37 | compatible = "fsl,mpc8272ads-mdio-bitbang", | ||
38 | "fsl,mpc8272-mdio-bitbang", | ||
39 | "fsl,cpm2-mdio-bitbang"; | ||
40 | reg = <10d40 14>; | ||
41 | #address-cells = <1>; | ||
42 | #size-cells = <0>; | ||
43 | fsl,mdio-pin = <12>; | ||
44 | fsl,mdc-pin = <13>; | ||
45 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt new file mode 100644 index 000000000000..4f8930263dd9 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt | |||
@@ -0,0 +1,115 @@ | |||
1 | * Freescale QUICC Engine module (QE) | ||
2 | This represents qe module that is installed on PowerQUICC II Pro. | ||
3 | |||
4 | NOTE: This is an interim binding; it should be updated to fit | ||
5 | in with the CPM binding later in this document. | ||
6 | |||
7 | Basically, it is a bus of devices, that could act more or less | ||
8 | as a complete entity (UCC, USB etc ). All of them should be siblings on | ||
9 | the "root" qe node, using the common properties from there. | ||
10 | The description below applies to the qe of MPC8360 and | ||
11 | more nodes and properties would be extended in the future. | ||
12 | |||
13 | i) Root QE device | ||
14 | |||
15 | Required properties: | ||
16 | - compatible : should be "fsl,qe"; | ||
17 | - model : precise model of the QE, Can be "QE", "CPM", or "CPM2" | ||
18 | - reg : offset and length of the device registers. | ||
19 | - bus-frequency : the clock frequency for QUICC Engine. | ||
20 | - fsl,qe-num-riscs: define how many RISC engines the QE has. | ||
21 | - fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the | ||
22 | threads. | ||
23 | |||
24 | Optional properties: | ||
25 | - fsl,firmware-phandle: | ||
26 | Usage: required only if there is no fsl,qe-firmware child node | ||
27 | Value type: <phandle> | ||
28 | Definition: Points to a firmware node (see "QE Firmware Node" below) | ||
29 | that contains the firmware that should be uploaded for this QE. | ||
30 | The compatible property for the firmware node should say, | ||
31 | "fsl,qe-firmware". | ||
32 | |||
33 | Recommended properties | ||
34 | - brg-frequency : the internal clock source frequency for baud-rate | ||
35 | generators in Hz. | ||
36 | |||
37 | Example: | ||
38 | qe@e0100000 { | ||
39 | #address-cells = <1>; | ||
40 | #size-cells = <1>; | ||
41 | #interrupt-cells = <2>; | ||
42 | compatible = "fsl,qe"; | ||
43 | ranges = <0 e0100000 00100000>; | ||
44 | reg = <e0100000 480>; | ||
45 | brg-frequency = <0>; | ||
46 | bus-frequency = <179A7B00>; | ||
47 | } | ||
48 | |||
49 | * Multi-User RAM (MURAM) | ||
50 | |||
51 | Required properties: | ||
52 | - compatible : should be "fsl,qe-muram", "fsl,cpm-muram". | ||
53 | - mode : the could be "host" or "slave". | ||
54 | - ranges : Should be defined as specified in 1) to describe the | ||
55 | translation of MURAM addresses. | ||
56 | - data-only : sub-node which defines the address area under MURAM | ||
57 | bus that can be allocated as data/parameter | ||
58 | |||
59 | Example: | ||
60 | |||
61 | muram@10000 { | ||
62 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; | ||
63 | ranges = <0 00010000 0000c000>; | ||
64 | |||
65 | data-only@0{ | ||
66 | compatible = "fsl,qe-muram-data", | ||
67 | "fsl,cpm-muram-data"; | ||
68 | reg = <0 c000>; | ||
69 | }; | ||
70 | }; | ||
71 | |||
72 | * QE Firmware Node | ||
73 | |||
74 | This node defines a firmware binary that is embedded in the device tree, for | ||
75 | the purpose of passing the firmware from bootloader to the kernel, or from | ||
76 | the hypervisor to the guest. | ||
77 | |||
78 | The firmware node itself contains the firmware binary contents, a compatible | ||
79 | property, and any firmware-specific properties. The node should be placed | ||
80 | inside a QE node that needs it. Doing so eliminates the need for a | ||
81 | fsl,firmware-phandle property. Other QE nodes that need the same firmware | ||
82 | should define an fsl,firmware-phandle property that points to the firmware node | ||
83 | in the first QE node. | ||
84 | |||
85 | The fsl,firmware property can be specified in the DTS (possibly using incbin) | ||
86 | or can be inserted by the boot loader at boot time. | ||
87 | |||
88 | Required properties: | ||
89 | - compatible | ||
90 | Usage: required | ||
91 | Value type: <string> | ||
92 | Definition: A standard property. Specify a string that indicates what | ||
93 | kind of firmware it is. For QE, this should be "fsl,qe-firmware". | ||
94 | |||
95 | - fsl,firmware | ||
96 | Usage: required | ||
97 | Value type: <prop-encoded-array>, encoded as an array of bytes | ||
98 | Definition: A standard property. This property contains the firmware | ||
99 | binary "blob". | ||
100 | |||
101 | Example: | ||
102 | qe1@e0080000 { | ||
103 | compatible = "fsl,qe"; | ||
104 | qe_firmware:qe-firmware { | ||
105 | compatible = "fsl,qe-firmware"; | ||
106 | fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; | ||
107 | }; | ||
108 | ... | ||
109 | }; | ||
110 | |||
111 | qe2@e0090000 { | ||
112 | compatible = "fsl,qe"; | ||
113 | fsl,firmware-phandle = <&qe_firmware>; | ||
114 | ... | ||
115 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt new file mode 100644 index 000000000000..249db3a15d15 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | * Uploaded QE firmware | ||
2 | |||
3 | If a new firmware has been uploaded to the QE (usually by the | ||
4 | boot loader), then a 'firmware' child node should be added to the QE | ||
5 | node. This node provides information on the uploaded firmware that | ||
6 | device drivers may need. | ||
7 | |||
8 | Required properties: | ||
9 | - id: The string name of the firmware. This is taken from the 'id' | ||
10 | member of the qe_firmware structure of the uploaded firmware. | ||
11 | Device drivers can search this string to determine if the | ||
12 | firmware they want is already present. | ||
13 | - extended-modes: The Extended Modes bitfield, taken from the | ||
14 | firmware binary. It is a 64-bit number represented | ||
15 | as an array of two 32-bit numbers. | ||
16 | - virtual-traps: The virtual traps, taken from the firmware binary. | ||
17 | It is an array of 8 32-bit numbers. | ||
18 | |||
19 | Example: | ||
20 | firmware { | ||
21 | id = "Soft-UART"; | ||
22 | extended-modes = <0 0>; | ||
23 | virtual-traps = <0 0 0 0 0 0 0 0>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt new file mode 100644 index 000000000000..60984260207b --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt | |||
@@ -0,0 +1,51 @@ | |||
1 | * Parallel I/O Ports | ||
2 | |||
3 | This node configures Parallel I/O ports for CPUs with QE support. | ||
4 | The node should reside in the "soc" node of the tree. For each | ||
5 | device that using parallel I/O ports, a child node should be created. | ||
6 | See the definition of the Pin configuration nodes below for more | ||
7 | information. | ||
8 | |||
9 | Required properties: | ||
10 | - device_type : should be "par_io". | ||
11 | - reg : offset to the register set and its length. | ||
12 | - num-ports : number of Parallel I/O ports | ||
13 | |||
14 | Example: | ||
15 | par_io@1400 { | ||
16 | reg = <1400 100>; | ||
17 | #address-cells = <1>; | ||
18 | #size-cells = <0>; | ||
19 | device_type = "par_io"; | ||
20 | num-ports = <7>; | ||
21 | ucc_pin@01 { | ||
22 | ...... | ||
23 | }; | ||
24 | |||
25 | Note that "par_io" nodes are obsolete, and should not be used for | ||
26 | the new device trees. Instead, each Par I/O bank should be represented | ||
27 | via its own gpio-controller node: | ||
28 | |||
29 | Required properties: | ||
30 | - #gpio-cells : should be "2". | ||
31 | - compatible : should be "fsl,<chip>-qe-pario-bank", | ||
32 | "fsl,mpc8323-qe-pario-bank". | ||
33 | - reg : offset to the register set and its length. | ||
34 | - gpio-controller : node to identify gpio controllers. | ||
35 | |||
36 | Example: | ||
37 | qe_pio_a: gpio-controller@1400 { | ||
38 | #gpio-cells = <2>; | ||
39 | compatible = "fsl,mpc8360-qe-pario-bank", | ||
40 | "fsl,mpc8323-qe-pario-bank"; | ||
41 | reg = <0x1400 0x18>; | ||
42 | gpio-controller; | ||
43 | }; | ||
44 | |||
45 | qe_pio_e: gpio-controller@1460 { | ||
46 | #gpio-cells = <2>; | ||
47 | compatible = "fsl,mpc8360-qe-pario-bank", | ||
48 | "fsl,mpc8323-qe-pario-bank"; | ||
49 | reg = <0x1460 0x18>; | ||
50 | gpio-controller; | ||
51 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt new file mode 100644 index 000000000000..c5b43061db3a --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt | |||
@@ -0,0 +1,60 @@ | |||
1 | * Pin configuration nodes | ||
2 | |||
3 | Required properties: | ||
4 | - linux,phandle : phandle of this node; likely referenced by a QE | ||
5 | device. | ||
6 | - pio-map : array of pin configurations. Each pin is defined by 6 | ||
7 | integers. The six numbers are respectively: port, pin, dir, | ||
8 | open_drain, assignment, has_irq. | ||
9 | - port : port number of the pin; 0-6 represent port A-G in UM. | ||
10 | - pin : pin number in the port. | ||
11 | - dir : direction of the pin, should encode as follows: | ||
12 | |||
13 | 0 = The pin is disabled | ||
14 | 1 = The pin is an output | ||
15 | 2 = The pin is an input | ||
16 | 3 = The pin is I/O | ||
17 | |||
18 | - open_drain : indicates the pin is normal or wired-OR: | ||
19 | |||
20 | 0 = The pin is actively driven as an output | ||
21 | 1 = The pin is an open-drain driver. As an output, the pin is | ||
22 | driven active-low, otherwise it is three-stated. | ||
23 | |||
24 | - assignment : function number of the pin according to the Pin Assignment | ||
25 | tables in User Manual. Each pin can have up to 4 possible functions in | ||
26 | QE and two options for CPM. | ||
27 | - has_irq : indicates if the pin is used as source of external | ||
28 | interrupts. | ||
29 | |||
30 | Example: | ||
31 | ucc_pin@01 { | ||
32 | linux,phandle = <140001>; | ||
33 | pio-map = < | ||
34 | /* port pin dir open_drain assignment has_irq */ | ||
35 | 0 3 1 0 1 0 /* TxD0 */ | ||
36 | 0 4 1 0 1 0 /* TxD1 */ | ||
37 | 0 5 1 0 1 0 /* TxD2 */ | ||
38 | 0 6 1 0 1 0 /* TxD3 */ | ||
39 | 1 6 1 0 3 0 /* TxD4 */ | ||
40 | 1 7 1 0 1 0 /* TxD5 */ | ||
41 | 1 9 1 0 2 0 /* TxD6 */ | ||
42 | 1 a 1 0 2 0 /* TxD7 */ | ||
43 | 0 9 2 0 1 0 /* RxD0 */ | ||
44 | 0 a 2 0 1 0 /* RxD1 */ | ||
45 | 0 b 2 0 1 0 /* RxD2 */ | ||
46 | 0 c 2 0 1 0 /* RxD3 */ | ||
47 | 0 d 2 0 1 0 /* RxD4 */ | ||
48 | 1 1 2 0 2 0 /* RxD5 */ | ||
49 | 1 0 2 0 2 0 /* RxD6 */ | ||
50 | 1 4 2 0 2 0 /* RxD7 */ | ||
51 | 0 7 1 0 1 0 /* TX_EN */ | ||
52 | 0 8 1 0 1 0 /* TX_ER */ | ||
53 | 0 f 2 0 1 0 /* RX_DV */ | ||
54 | 0 10 2 0 1 0 /* RX_ER */ | ||
55 | 0 0 2 0 1 0 /* RX_CLK */ | ||
56 | 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ | ||
57 | 2 8 2 0 1 0>; /* GTX125 - CLK9 */ | ||
58 | }; | ||
59 | |||
60 | |||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt new file mode 100644 index 000000000000..e47734bee3f0 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt | |||
@@ -0,0 +1,70 @@ | |||
1 | * UCC (Unified Communications Controllers) | ||
2 | |||
3 | Required properties: | ||
4 | - device_type : should be "network", "hldc", "uart", "transparent" | ||
5 | "bisync", "atm", or "serial". | ||
6 | - compatible : could be "ucc_geth" or "fsl_atm" and so on. | ||
7 | - cell-index : the ucc number(1-8), corresponding to UCCx in UM. | ||
8 | - reg : Offset and length of the register set for the device | ||
9 | - interrupts : <a b> where a is the interrupt number and b is a | ||
10 | field that represents an encoding of the sense and level | ||
11 | information for the interrupt. This should be encoded based on | ||
12 | the information in section 2) depending on the type of interrupt | ||
13 | controller you have. | ||
14 | - interrupt-parent : the phandle for the interrupt controller that | ||
15 | services interrupts for this device. | ||
16 | - pio-handle : The phandle for the Parallel I/O port configuration. | ||
17 | - port-number : for UART drivers, the port number to use, between 0 and 3. | ||
18 | This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0. | ||
19 | The port number is added to the minor number of the device. Unlike the | ||
20 | CPM UART driver, the port-number is required for the QE UART driver. | ||
21 | - soft-uart : for UART drivers, if specified this means the QE UART device | ||
22 | driver should use "Soft-UART" mode, which is needed on some SOCs that have | ||
23 | broken UART hardware. Soft-UART is provided via a microcode upload. | ||
24 | - rx-clock-name: the UCC receive clock source | ||
25 | "none": clock source is disabled | ||
26 | "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
27 | "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
28 | - tx-clock-name: the UCC transmit clock source | ||
29 | "none": clock source is disabled | ||
30 | "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
31 | "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
32 | The following two properties are deprecated. rx-clock has been replaced | ||
33 | with rx-clock-name, and tx-clock has been replaced with tx-clock-name. | ||
34 | Drivers that currently use the deprecated properties should continue to | ||
35 | do so, in order to support older device trees, but they should be updated | ||
36 | to check for the new properties first. | ||
37 | - rx-clock : represents the UCC receive clock source. | ||
38 | 0x00 : clock source is disabled; | ||
39 | 0x1~0x10 : clock source is BRG1~BRG16 respectively; | ||
40 | 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively. | ||
41 | - tx-clock: represents the UCC transmit clock source; | ||
42 | 0x00 : clock source is disabled; | ||
43 | 0x1~0x10 : clock source is BRG1~BRG16 respectively; | ||
44 | 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively. | ||
45 | |||
46 | Required properties for network device_type: | ||
47 | - mac-address : list of bytes representing the ethernet address. | ||
48 | - phy-handle : The phandle for the PHY connected to this controller. | ||
49 | |||
50 | Recommended properties: | ||
51 | - phy-connection-type : a string naming the controller/PHY interface type, | ||
52 | i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal | ||
53 | Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only), | ||
54 | "tbi", or "rtbi". | ||
55 | |||
56 | Example: | ||
57 | ucc@2000 { | ||
58 | device_type = "network"; | ||
59 | compatible = "ucc_geth"; | ||
60 | cell-index = <1>; | ||
61 | reg = <2000 200>; | ||
62 | interrupts = <a0 0>; | ||
63 | interrupt-parent = <700>; | ||
64 | mac-address = [ 00 04 9f 00 23 23 ]; | ||
65 | rx-clock = "none"; | ||
66 | tx-clock = "clk9"; | ||
67 | phy-handle = <212000>; | ||
68 | phy-connection-type = "gmii"; | ||
69 | pio-handle = <140001>; | ||
70 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt new file mode 100644 index 000000000000..9ccd5f30405b --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt | |||
@@ -0,0 +1,37 @@ | |||
1 | Freescale QUICC Engine USB Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb". | ||
5 | - reg : the first two cells should contain usb registers location and | ||
6 | length, the next two two cells should contain PRAM location and | ||
7 | length. | ||
8 | - interrupts : should contain USB interrupt. | ||
9 | - interrupt-parent : interrupt source phandle. | ||
10 | - fsl,fullspeed-clock : specifies the full speed USB clock source: | ||
11 | "none": clock source is disabled | ||
12 | "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
13 | "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
14 | - fsl,lowspeed-clock : specifies the low speed USB clock source: | ||
15 | "none": clock source is disabled | ||
16 | "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
17 | "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
18 | - hub-power-budget : USB power budget for the root hub, in mA. | ||
19 | - gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP, | ||
20 | USBRN, SPEED (optional), and POWER (optional). | ||
21 | |||
22 | Example: | ||
23 | |||
24 | usb@6c0 { | ||
25 | compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb"; | ||
26 | reg = <0x6c0 0x40 0x8b00 0x100>; | ||
27 | interrupts = <11>; | ||
28 | interrupt-parent = <&qeic>; | ||
29 | fsl,fullspeed-clock = "clk21"; | ||
30 | gpios = <&qe_pio_b 2 0 /* USBOE */ | ||
31 | &qe_pio_b 3 0 /* USBTP */ | ||
32 | &qe_pio_b 8 0 /* USBTN */ | ||
33 | &qe_pio_b 9 0 /* USBRP */ | ||
34 | &qe_pio_b 11 0 /* USBRN */ | ||
35 | &qe_pio_e 20 0 /* SPEED */ | ||
36 | &qe_pio_e 21 0 /* POWER */>; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt new file mode 100644 index 000000000000..2ea76d9d137c --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt | |||
@@ -0,0 +1,32 @@ | |||
1 | * Serial | ||
2 | |||
3 | Currently defined compatibles: | ||
4 | - fsl,cpm1-smc-uart | ||
5 | - fsl,cpm2-smc-uart | ||
6 | - fsl,cpm1-scc-uart | ||
7 | - fsl,cpm2-scc-uart | ||
8 | - fsl,qe-uart | ||
9 | |||
10 | Modem control lines connected to GPIO controllers are listed in the gpios | ||
11 | property as described in booting-without-of.txt, section IX.1 in the following | ||
12 | order: | ||
13 | |||
14 | CTS, RTS, DCD, DSR, DTR, and RI. | ||
15 | |||
16 | The gpios property is optional and can be left out when control lines are | ||
17 | not used. | ||
18 | |||
19 | Example: | ||
20 | |||
21 | serial@11a00 { | ||
22 | device_type = "serial"; | ||
23 | compatible = "fsl,mpc8272-scc-uart", | ||
24 | "fsl,cpm2-scc-uart"; | ||
25 | reg = <11a00 20 8000 100>; | ||
26 | interrupts = <28 8>; | ||
27 | interrupt-parent = <&PIC>; | ||
28 | fsl,cpm-brg = <1>; | ||
29 | fsl,cpm-command = <00800000>; | ||
30 | gpios = <&gpio_c 15 0 | ||
31 | &gpio_d 29 0>; | ||
32 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt new file mode 100644 index 000000000000..b66cb6d31d69 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt | |||
@@ -0,0 +1,34 @@ | |||
1 | * Freescale Display Interface Unit | ||
2 | |||
3 | The Freescale DIU is a LCD controller, with proper hardware, it can also | ||
4 | drive DVI monitors. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : should be "fsl,diu" or "fsl,mpc5121-diu". | ||
8 | - reg : should contain at least address and length of the DIU register | ||
9 | set. | ||
10 | - interrupts : one DIU interrupt should be described here. | ||
11 | - interrupt-parent : the phandle for the interrupt controller that | ||
12 | services interrupts for this device. | ||
13 | |||
14 | Optional properties: | ||
15 | - edid : verbatim EDID data block describing attached display. | ||
16 | Data from the detailed timing descriptor will be used to | ||
17 | program the display controller. | ||
18 | |||
19 | Example (MPC8610HPCD): | ||
20 | display@2c000 { | ||
21 | compatible = "fsl,diu"; | ||
22 | reg = <0x2c000 100>; | ||
23 | interrupts = <72 2>; | ||
24 | interrupt-parent = <&mpic>; | ||
25 | }; | ||
26 | |||
27 | Example for MPC5121: | ||
28 | display@2100 { | ||
29 | compatible = "fsl,mpc5121-diu"; | ||
30 | reg = <0x2100 0x100>; | ||
31 | interrupts = <64 0x8>; | ||
32 | interrupt-parent = <&ipic>; | ||
33 | edid = [edid-data]; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt new file mode 100644 index 000000000000..2a4b4bce6110 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt | |||
@@ -0,0 +1,144 @@ | |||
1 | * Freescale 83xx DMA Controller | ||
2 | |||
3 | Freescale PowerPC 83xx have on chip general purpose DMA controllers. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : compatible list, contains 2 entries, first is | ||
8 | "fsl,CHIP-dma", where CHIP is the processor | ||
9 | (mpc8349, mpc8360, etc.) and the second is | ||
10 | "fsl,elo-dma" | ||
11 | - reg : <registers mapping for DMA general status reg> | ||
12 | - ranges : Should be defined as specified in 1) to describe the | ||
13 | DMA controller channels. | ||
14 | - cell-index : controller index. 0 for controller @ 0x8100 | ||
15 | - interrupts : <interrupt mapping for DMA IRQ> | ||
16 | - interrupt-parent : optional, if needed for interrupt mapping | ||
17 | |||
18 | |||
19 | - DMA channel nodes: | ||
20 | - compatible : compatible list, contains 2 entries, first is | ||
21 | "fsl,CHIP-dma-channel", where CHIP is the processor | ||
22 | (mpc8349, mpc8350, etc.) and the second is | ||
23 | "fsl,elo-dma-channel". However, see note below. | ||
24 | - reg : <registers mapping for channel> | ||
25 | - cell-index : dma channel index starts at 0. | ||
26 | |||
27 | Optional properties: | ||
28 | - interrupts : <interrupt mapping for DMA channel IRQ> | ||
29 | (on 83xx this is expected to be identical to | ||
30 | the interrupts property of the parent node) | ||
31 | - interrupt-parent : optional, if needed for interrupt mapping | ||
32 | |||
33 | Example: | ||
34 | dma@82a8 { | ||
35 | #address-cells = <1>; | ||
36 | #size-cells = <1>; | ||
37 | compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; | ||
38 | reg = <0x82a8 4>; | ||
39 | ranges = <0 0x8100 0x1a4>; | ||
40 | interrupt-parent = <&ipic>; | ||
41 | interrupts = <71 8>; | ||
42 | cell-index = <0>; | ||
43 | dma-channel@0 { | ||
44 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; | ||
45 | cell-index = <0>; | ||
46 | reg = <0 0x80>; | ||
47 | interrupt-parent = <&ipic>; | ||
48 | interrupts = <71 8>; | ||
49 | }; | ||
50 | dma-channel@80 { | ||
51 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; | ||
52 | cell-index = <1>; | ||
53 | reg = <0x80 0x80>; | ||
54 | interrupt-parent = <&ipic>; | ||
55 | interrupts = <71 8>; | ||
56 | }; | ||
57 | dma-channel@100 { | ||
58 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; | ||
59 | cell-index = <2>; | ||
60 | reg = <0x100 0x80>; | ||
61 | interrupt-parent = <&ipic>; | ||
62 | interrupts = <71 8>; | ||
63 | }; | ||
64 | dma-channel@180 { | ||
65 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; | ||
66 | cell-index = <3>; | ||
67 | reg = <0x180 0x80>; | ||
68 | interrupt-parent = <&ipic>; | ||
69 | interrupts = <71 8>; | ||
70 | }; | ||
71 | }; | ||
72 | |||
73 | * Freescale 85xx/86xx DMA Controller | ||
74 | |||
75 | Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. | ||
76 | |||
77 | Required properties: | ||
78 | |||
79 | - compatible : compatible list, contains 2 entries, first is | ||
80 | "fsl,CHIP-dma", where CHIP is the processor | ||
81 | (mpc8540, mpc8540, etc.) and the second is | ||
82 | "fsl,eloplus-dma" | ||
83 | - reg : <registers mapping for DMA general status reg> | ||
84 | - cell-index : controller index. 0 for controller @ 0x21000, | ||
85 | 1 for controller @ 0xc000 | ||
86 | - ranges : Should be defined as specified in 1) to describe the | ||
87 | DMA controller channels. | ||
88 | |||
89 | - DMA channel nodes: | ||
90 | - compatible : compatible list, contains 2 entries, first is | ||
91 | "fsl,CHIP-dma-channel", where CHIP is the processor | ||
92 | (mpc8540, mpc8560, etc.) and the second is | ||
93 | "fsl,eloplus-dma-channel". However, see note below. | ||
94 | - cell-index : dma channel index starts at 0. | ||
95 | - reg : <registers mapping for channel> | ||
96 | - interrupts : <interrupt mapping for DMA channel IRQ> | ||
97 | - interrupt-parent : optional, if needed for interrupt mapping | ||
98 | |||
99 | Example: | ||
100 | dma@21300 { | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <1>; | ||
103 | compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; | ||
104 | reg = <0x21300 4>; | ||
105 | ranges = <0 0x21100 0x200>; | ||
106 | cell-index = <0>; | ||
107 | dma-channel@0 { | ||
108 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; | ||
109 | reg = <0 0x80>; | ||
110 | cell-index = <0>; | ||
111 | interrupt-parent = <&mpic>; | ||
112 | interrupts = <20 2>; | ||
113 | }; | ||
114 | dma-channel@80 { | ||
115 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; | ||
116 | reg = <0x80 0x80>; | ||
117 | cell-index = <1>; | ||
118 | interrupt-parent = <&mpic>; | ||
119 | interrupts = <21 2>; | ||
120 | }; | ||
121 | dma-channel@100 { | ||
122 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; | ||
123 | reg = <0x100 0x80>; | ||
124 | cell-index = <2>; | ||
125 | interrupt-parent = <&mpic>; | ||
126 | interrupts = <22 2>; | ||
127 | }; | ||
128 | dma-channel@180 { | ||
129 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; | ||
130 | reg = <0x180 0x80>; | ||
131 | cell-index = <3>; | ||
132 | interrupt-parent = <&mpic>; | ||
133 | interrupts = <23 2>; | ||
134 | }; | ||
135 | }; | ||
136 | |||
137 | Note on DMA channel compatible properties: The compatible property must say | ||
138 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA | ||
139 | driver (fsldma). Any DMA channel used by fsldma cannot be used by another | ||
140 | DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA | ||
141 | channel that should be used for another driver should not use | ||
142 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for | ||
143 | example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt | ||
144 | for more information. | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt b/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt new file mode 100644 index 000000000000..f514f29c67d6 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt | |||
@@ -0,0 +1,64 @@ | |||
1 | ===================================================================== | ||
2 | E500 LAW & Coherency Module Device Tree Binding | ||
3 | Copyright (C) 2009 Freescale Semiconductor Inc. | ||
4 | ===================================================================== | ||
5 | |||
6 | Local Access Window (LAW) Node | ||
7 | |||
8 | The LAW node represents the region of CCSR space where local access | ||
9 | windows are configured. For ECM based devices this is the first 4k | ||
10 | of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some | ||
11 | number of local access windows as specified by fsl,num-laws. | ||
12 | |||
13 | PROPERTIES | ||
14 | |||
15 | - compatible | ||
16 | Usage: required | ||
17 | Value type: <string> | ||
18 | Definition: Must include "fsl,ecm-law" | ||
19 | |||
20 | - reg | ||
21 | Usage: required | ||
22 | Value type: <prop-encoded-array> | ||
23 | Definition: A standard property. The value specifies the | ||
24 | physical address offset and length of the CCSR space | ||
25 | registers. | ||
26 | |||
27 | - fsl,num-laws | ||
28 | Usage: required | ||
29 | Value type: <u32> | ||
30 | Definition: The value specifies the number of local access | ||
31 | windows for this device. | ||
32 | |||
33 | ===================================================================== | ||
34 | |||
35 | E500 Coherency Module Node | ||
36 | |||
37 | The E500 LAW node represents the region of CCSR space where ECM config | ||
38 | and error reporting registers exist, this is the second 4k (0x1000) | ||
39 | of CCSR space. | ||
40 | |||
41 | PROPERTIES | ||
42 | |||
43 | - compatible | ||
44 | Usage: required | ||
45 | Value type: <string> | ||
46 | Definition: Must include "fsl,CHIP-ecm", "fsl,ecm" where | ||
47 | CHIP is the processor (mpc8572, mpc8544, etc.) | ||
48 | |||
49 | - reg | ||
50 | Usage: required | ||
51 | Value type: <prop-encoded-array> | ||
52 | Definition: A standard property. The value specifies the | ||
53 | physical address offset and length of the CCSR space | ||
54 | registers. | ||
55 | |||
56 | - interrupts | ||
57 | Usage: required | ||
58 | Value type: <prop-encoded-array> | ||
59 | |||
60 | - interrupt-parent | ||
61 | Usage: required | ||
62 | Value type: <phandle> | ||
63 | |||
64 | ===================================================================== | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt b/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt new file mode 100644 index 000000000000..9a33efded4bc --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt | |||
@@ -0,0 +1,31 @@ | |||
1 | * Freescale General-purpose Timers Module | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be | ||
5 | "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs | ||
6 | "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs | ||
7 | "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs | ||
8 | - reg : should contain gtm registers location and length (0x40). | ||
9 | - interrupts : should contain four interrupts. | ||
10 | - interrupt-parent : interrupt source phandle. | ||
11 | - clock-frequency : specifies the frequency driving the timer. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | timer@500 { | ||
16 | compatible = "fsl,mpc8360-gtm", "fsl,gtm"; | ||
17 | reg = <0x500 0x40>; | ||
18 | interrupts = <90 8 78 8 84 8 72 8>; | ||
19 | interrupt-parent = <&ipic>; | ||
20 | /* filled by u-boot */ | ||
21 | clock-frequency = <0>; | ||
22 | }; | ||
23 | |||
24 | timer@440 { | ||
25 | compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; | ||
26 | reg = <0x440 0x40>; | ||
27 | interrupts = <12 13 14 15>; | ||
28 | interrupt-parent = <&qeic>; | ||
29 | /* filled by u-boot */ | ||
30 | clock-frequency = <0>; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt new file mode 100644 index 000000000000..9e7a2417dac5 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | * Global Utilities Block | ||
2 | |||
3 | The global utilities block controls power management, I/O device | ||
4 | enabling, power-on-reset configuration monitoring, general-purpose | ||
5 | I/O signal configuration, alternate function selection for multiplexed | ||
6 | signals, and clock control. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible : Should define the compatible device type for | ||
11 | global-utilities. | ||
12 | - reg : Offset and length of the register set for the device. | ||
13 | |||
14 | Recommended properties: | ||
15 | |||
16 | - fsl,has-rstcr : Indicates that the global utilities register set | ||
17 | contains a functioning "reset control register" (i.e. the board | ||
18 | is wired to reset upon setting the HRESET_REQ bit in this register). | ||
19 | |||
20 | Example: | ||
21 | global-utilities@e0000 { /* global utilities block */ | ||
22 | compatible = "fsl,mpc8548-guts"; | ||
23 | reg = <e0000 1000>; | ||
24 | fsl,has-rstcr; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt new file mode 100644 index 000000000000..3300fec501c5 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt | |||
@@ -0,0 +1,35 @@ | |||
1 | * Chipselect/Local Bus | ||
2 | |||
3 | Properties: | ||
4 | - name : Should be localbus | ||
5 | - #address-cells : Should be either two or three. The first cell is the | ||
6 | chipselect number, and the remaining cells are the | ||
7 | offset into the chipselect. | ||
8 | - #size-cells : Either one or two, depending on how large each chipselect | ||
9 | can be. | ||
10 | - ranges : Each range corresponds to a single chipselect, and cover | ||
11 | the entire access window as configured. | ||
12 | |||
13 | Example: | ||
14 | localbus@f0010100 { | ||
15 | compatible = "fsl,mpc8272-localbus", | ||
16 | "fsl,pq2-localbus"; | ||
17 | #address-cells = <2>; | ||
18 | #size-cells = <1>; | ||
19 | reg = <f0010100 40>; | ||
20 | |||
21 | ranges = <0 0 fe000000 02000000 | ||
22 | 1 0 f4500000 00008000>; | ||
23 | |||
24 | flash@0,0 { | ||
25 | compatible = "jedec-flash"; | ||
26 | reg = <0 0 2000000>; | ||
27 | bank-width = <4>; | ||
28 | device-width = <1>; | ||
29 | }; | ||
30 | |||
31 | board-control@1,0 { | ||
32 | reg = <1 0 20>; | ||
33 | compatible = "fsl,mpc8272ads-bcsr"; | ||
34 | }; | ||
35 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt new file mode 100644 index 000000000000..4ceda9b3b413 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt | |||
@@ -0,0 +1,64 @@ | |||
1 | ===================================================================== | ||
2 | MPX LAW & Coherency Module Device Tree Binding | ||
3 | Copyright (C) 2009 Freescale Semiconductor Inc. | ||
4 | ===================================================================== | ||
5 | |||
6 | Local Access Window (LAW) Node | ||
7 | |||
8 | The LAW node represents the region of CCSR space where local access | ||
9 | windows are configured. For MCM based devices this is the first 4k | ||
10 | of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some | ||
11 | number of local access windows as specified by fsl,num-laws. | ||
12 | |||
13 | PROPERTIES | ||
14 | |||
15 | - compatible | ||
16 | Usage: required | ||
17 | Value type: <string> | ||
18 | Definition: Must include "fsl,mcm-law" | ||
19 | |||
20 | - reg | ||
21 | Usage: required | ||
22 | Value type: <prop-encoded-array> | ||
23 | Definition: A standard property. The value specifies the | ||
24 | physical address offset and length of the CCSR space | ||
25 | registers. | ||
26 | |||
27 | - fsl,num-laws | ||
28 | Usage: required | ||
29 | Value type: <u32> | ||
30 | Definition: The value specifies the number of local access | ||
31 | windows for this device. | ||
32 | |||
33 | ===================================================================== | ||
34 | |||
35 | MPX Coherency Module Node | ||
36 | |||
37 | The MPX LAW node represents the region of CCSR space where MCM config | ||
38 | and error reporting registers exist, this is the second 4k (0x1000) | ||
39 | of CCSR space. | ||
40 | |||
41 | PROPERTIES | ||
42 | |||
43 | - compatible | ||
44 | Usage: required | ||
45 | Value type: <string> | ||
46 | Definition: Must include "fsl,CHIP-mcm", "fsl,mcm" where | ||
47 | CHIP is the processor (mpc8641, mpc8610, etc.) | ||
48 | |||
49 | - reg | ||
50 | Usage: required | ||
51 | Value type: <prop-encoded-array> | ||
52 | Definition: A standard property. The value specifies the | ||
53 | physical address offset and length of the CCSR space | ||
54 | registers. | ||
55 | |||
56 | - interrupts | ||
57 | Usage: required | ||
58 | Value type: <prop-encoded-array> | ||
59 | |||
60 | - interrupt-parent | ||
61 | Usage: required | ||
62 | Value type: <phandle> | ||
63 | |||
64 | ===================================================================== | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt new file mode 100644 index 000000000000..0f766333b6eb --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx". | ||
5 | - reg : should specify I2C address (0x0a). | ||
6 | - #gpio-cells : should be 2. | ||
7 | - gpio-controller : should be present. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | mcu@0a { | ||
12 | #gpio-cells = <2>; | ||
13 | compatible = "fsl,mc9s08qg8-mpc8349emitx", | ||
14 | "fsl,mcu-mpc8349emitx"; | ||
15 | reg = <0x0a>; | ||
16 | gpio-controller; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt new file mode 100644 index 000000000000..8832e8798912 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt | |||
@@ -0,0 +1,70 @@ | |||
1 | MPC5121 PSC Device Tree Bindings | ||
2 | |||
3 | PSC in UART mode | ||
4 | ---------------- | ||
5 | |||
6 | For PSC in UART mode the needed PSC serial devices | ||
7 | are specified by fsl,mpc5121-psc-uart nodes in the | ||
8 | fsl,mpc5121-immr SoC node. Additionally the PSC FIFO | ||
9 | Controller node fsl,mpc5121-psc-fifo is requered there: | ||
10 | |||
11 | fsl,mpc5121-psc-uart nodes | ||
12 | -------------------------- | ||
13 | |||
14 | Required properties : | ||
15 | - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc" | ||
16 | - cell-index : Index of the PSC in hardware | ||
17 | - reg : Offset and length of the register set for the PSC device | ||
18 | - interrupts : <a b> where a is the interrupt number of the | ||
19 | PSC FIFO Controller and b is a field that represents an | ||
20 | encoding of the sense and level information for the interrupt. | ||
21 | - interrupt-parent : the phandle for the interrupt controller that | ||
22 | services interrupts for this device. | ||
23 | |||
24 | Recommended properties : | ||
25 | - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) | ||
26 | - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) | ||
27 | |||
28 | |||
29 | fsl,mpc5121-psc-fifo node | ||
30 | ------------------------- | ||
31 | |||
32 | Required properties : | ||
33 | - compatible : Should be "fsl,mpc5121-psc-fifo" | ||
34 | - reg : Offset and length of the register set for the PSC | ||
35 | FIFO Controller | ||
36 | - interrupts : <a b> where a is the interrupt number of the | ||
37 | PSC FIFO Controller and b is a field that represents an | ||
38 | encoding of the sense and level information for the interrupt. | ||
39 | - interrupt-parent : the phandle for the interrupt controller that | ||
40 | services interrupts for this device. | ||
41 | |||
42 | |||
43 | Example for a board using PSC0 and PSC1 devices in serial mode: | ||
44 | |||
45 | serial@11000 { | ||
46 | compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
47 | cell-index = <0>; | ||
48 | reg = <0x11000 0x100>; | ||
49 | interrupts = <40 0x8>; | ||
50 | interrupt-parent = < &ipic >; | ||
51 | fsl,rx-fifo-size = <16>; | ||
52 | fsl,tx-fifo-size = <16>; | ||
53 | }; | ||
54 | |||
55 | serial@11100 { | ||
56 | compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
57 | cell-index = <1>; | ||
58 | reg = <0x11100 0x100>; | ||
59 | interrupts = <40 0x8>; | ||
60 | interrupt-parent = < &ipic >; | ||
61 | fsl,rx-fifo-size = <16>; | ||
62 | fsl,tx-fifo-size = <16>; | ||
63 | }; | ||
64 | |||
65 | pscfifo@11f00 { | ||
66 | compatible = "fsl,mpc5121-psc-fifo"; | ||
67 | reg = <0x11f00 0x100>; | ||
68 | interrupts = <40 0x8>; | ||
69 | interrupt-parent = < &ipic >; | ||
70 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt new file mode 100644 index 000000000000..4ccb2cd5df94 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt | |||
@@ -0,0 +1,198 @@ | |||
1 | MPC5200 Device Tree Bindings | ||
2 | ---------------------------- | ||
3 | |||
4 | (c) 2006-2009 Secret Lab Technologies Ltd | ||
5 | Grant Likely <grant.likely@secretlab.ca> | ||
6 | |||
7 | Naming conventions | ||
8 | ------------------ | ||
9 | For mpc5200 on-chip devices, the format for each compatible value is | ||
10 | <chip>-<device>[-<mode>]. The OS should be able to match a device driver | ||
11 | to the device based solely on the compatible value. If two drivers | ||
12 | match on the compatible list; the 'most compatible' driver should be | ||
13 | selected. | ||
14 | |||
15 | The split between the MPC5200 and the MPC5200B leaves a bit of a | ||
16 | conundrum. How should the compatible property be set up to provide | ||
17 | maximum compatibility information; but still accurately describe the | ||
18 | chip? For the MPC5200; the answer is easy. Most of the SoC devices | ||
19 | originally appeared on the MPC5200. Since they didn't exist anywhere | ||
20 | else; the 5200 compatible properties will contain only one item; | ||
21 | "fsl,mpc5200-<device>". | ||
22 | |||
23 | The 5200B is almost the same as the 5200, but not quite. It fixes | ||
24 | silicon bugs and it adds a small number of enhancements. Most of the | ||
25 | devices either provide exactly the same interface as on the 5200. A few | ||
26 | devices have extra functions but still have a backwards compatible mode. | ||
27 | To express this information as completely as possible, 5200B device trees | ||
28 | should have two items in the compatible list: | ||
29 | compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>"; | ||
30 | |||
31 | It is *strongly* recommended that 5200B device trees follow this convention | ||
32 | (instead of only listing the base mpc5200 item). | ||
33 | |||
34 | ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec"; | ||
35 | ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec"; | ||
36 | |||
37 | Modal devices, like PSCs, also append the configured function to the | ||
38 | end of the compatible field. ie. A PSC in i2s mode would specify | ||
39 | "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to | ||
40 | avoid naming conflicts with non-psc devices providing the same | ||
41 | function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe | ||
42 | the mpc5200 simple spi device and a PSC spi mode respectively. | ||
43 | |||
44 | At the time of writing, exact chip may be either 'fsl,mpc5200' or | ||
45 | 'fsl,mpc5200b'. | ||
46 | |||
47 | The soc node | ||
48 | ------------ | ||
49 | This node describes the on chip SOC peripherals. Every mpc5200 based | ||
50 | board will have this node, and as such there is a common naming | ||
51 | convention for SOC devices. | ||
52 | |||
53 | Required properties: | ||
54 | name description | ||
55 | ---- ----------- | ||
56 | ranges Memory range of the internal memory mapped registers. | ||
57 | Should be <0 [baseaddr] 0xc000> | ||
58 | reg Should be <[baseaddr] 0x100> | ||
59 | compatible mpc5200: "fsl,mpc5200-immr" | ||
60 | mpc5200b: "fsl,mpc5200b-immr" | ||
61 | system-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI | ||
62 | clocks are derived from the fsystem clock. | ||
63 | bus-frequency IPB bus frequency in Hz. Clock rate | ||
64 | used by most of the soc devices. | ||
65 | |||
66 | soc child nodes | ||
67 | --------------- | ||
68 | Any on chip SOC devices available to Linux must appear as soc5200 child nodes. | ||
69 | |||
70 | Note: The tables below show the value for the mpc5200. A mpc5200b device | ||
71 | tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form. | ||
72 | |||
73 | Required soc5200 child nodes: | ||
74 | name compatible Description | ||
75 | ---- ---------- ----------- | ||
76 | cdm@<addr> fsl,mpc5200-cdm Clock Distribution | ||
77 | interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt | ||
78 | controller to boot | ||
79 | bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller | ||
80 | |||
81 | Recommended soc5200 child nodes; populate as needed for your board | ||
82 | name compatible Description | ||
83 | ---- ---------- ----------- | ||
84 | timer@<addr> fsl,mpc5200-gpt General purpose timers | ||
85 | gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller | ||
86 | gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller | ||
87 | rtc@<addr> fsl,mpc5200-rtc Real time clock | ||
88 | mscan@<addr> fsl,mpc5200-mscan CAN bus controller | ||
89 | pci@<addr> fsl,mpc5200-pci PCI bridge | ||
90 | serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode | ||
91 | i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode | ||
92 | ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode | ||
93 | spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode | ||
94 | irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode | ||
95 | spi@<addr> fsl,mpc5200-spi MPC5200 spi device | ||
96 | ethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device | ||
97 | ata@<addr> fsl,mpc5200-ata IDE ATA interface | ||
98 | i2c@<addr> fsl,mpc5200-i2c I2C controller | ||
99 | usb@<addr> fsl,mpc5200-ohci,ohci-be USB controller | ||
100 | xlb@<addr> fsl,mpc5200-xlb XLB arbitrator | ||
101 | |||
102 | fsl,mpc5200-gpt nodes | ||
103 | --------------------- | ||
104 | On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board | ||
105 | design supports the internal wdt, then the device node for GPT0 should | ||
106 | include the empty property 'fsl,has-wdt'. Note that this does not activate | ||
107 | the watchdog. The timer will function as a GPT if the timer api is used, and | ||
108 | it will function as watchdog if the watchdog device is used. The watchdog | ||
109 | mode has priority over the gpt mode, i.e. if the watchdog is activated, any | ||
110 | gpt api call to this timer will fail with -EBUSY. | ||
111 | |||
112 | If you add the property | ||
113 | fsl,wdt-on-boot = <n>; | ||
114 | GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it. | ||
115 | If n>0, the watchdog is started with a timeout of n seconds. If n=0, the | ||
116 | configuration of the watchdog is not touched. This is useful in two cases: | ||
117 | - just mark GPT0 as watchdog, blocking gpt accesses, and configure it later; | ||
118 | - do not touch a configuration assigned by the boot loader which supervises | ||
119 | the boot process itself. | ||
120 | |||
121 | The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option. | ||
122 | |||
123 | An mpc5200-gpt can be used as a single line GPIO controller. To do so, | ||
124 | add the following properties to the gpt node: | ||
125 | gpio-controller; | ||
126 | #gpio-cells = <2>; | ||
127 | When referencing the GPIO line from another node, the first cell must always | ||
128 | be zero and the second cell represents the gpio flags and described in the | ||
129 | gpio device tree binding. | ||
130 | |||
131 | An mpc5200-gpt can be used as a single line edge sensitive interrupt | ||
132 | controller. To do so, add the following properties to the gpt node: | ||
133 | interrupt-controller; | ||
134 | #interrupt-cells = <1>; | ||
135 | When referencing the IRQ line from another node, the cell represents the | ||
136 | sense mode; 1 for edge rising, 2 for edge falling. | ||
137 | |||
138 | fsl,mpc5200-psc nodes | ||
139 | --------------------- | ||
140 | The PSCs should include a cell-index which is the index of the PSC in | ||
141 | hardware. cell-index is used to determine which shared SoC registers to | ||
142 | use when setting up PSC clocking. cell-index number starts at '0'. ie: | ||
143 | PSC1 has 'cell-index = <0>' | ||
144 | PSC4 has 'cell-index = <3>' | ||
145 | |||
146 | PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in | ||
147 | i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the | ||
148 | compatible field. | ||
149 | |||
150 | |||
151 | fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes | ||
152 | ------------------------------------------------ | ||
153 | Each GPIO controller node should have the empty property gpio-controller and | ||
154 | #gpio-cells set to 2. First cell is the GPIO number which is interpreted | ||
155 | according to the bit numbers in the GPIO control registers. The second cell | ||
156 | is for flags which is currently unused. | ||
157 | |||
158 | fsl,mpc5200-fec nodes | ||
159 | --------------------- | ||
160 | The FEC node can specify one of the following properties to configure | ||
161 | the MII link: | ||
162 | - fsl,7-wire-mode - An empty property that specifies the link uses 7-wire | ||
163 | mode instead of MII | ||
164 | - current-speed - Specifies that the MII should be configured for a fixed | ||
165 | speed. This property should contain two cells. The | ||
166 | first cell specifies the speed in Mbps and the second | ||
167 | should be '0' for half duplex and '1' for full duplex | ||
168 | - phy-handle - Contains a phandle to an Ethernet PHY. | ||
169 | |||
170 | Interrupt controller (fsl,mpc5200-pic) node | ||
171 | ------------------------------------------- | ||
172 | The mpc5200 pic binding splits hardware IRQ numbers into two levels. The | ||
173 | split reflects the layout of the PIC hardware itself, which groups | ||
174 | interrupts into one of three groups; CRIT, MAIN or PERP. Also, the | ||
175 | Bestcomm dma engine has it's own set of interrupt sources which are | ||
176 | cascaded off of peripheral interrupt 0, which the driver interprets as a | ||
177 | fourth group, SDMA. | ||
178 | |||
179 | The interrupts property for device nodes using the mpc5200 pic consists | ||
180 | of three cells; <L1 L2 level> | ||
181 | |||
182 | L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3] | ||
183 | L2 := interrupt number; directly mapped from the value in the | ||
184 | "ICTL PerStat, MainStat, CritStat Encoded Register" | ||
185 | level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3] | ||
186 | |||
187 | For external IRQs, use the following interrupt property values (how to | ||
188 | specify external interrupts is a frequently asked question): | ||
189 | External interrupts: | ||
190 | external irq0: interrupts = <0 0 n>; | ||
191 | external irq1: interrupts = <1 1 n>; | ||
192 | external irq2: interrupts = <1 2 n>; | ||
193 | external irq3: interrupts = <1 3 n>; | ||
194 | 'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) | ||
195 | |||
196 | fsl,mpc5200-mscan nodes | ||
197 | ----------------------- | ||
198 | See file can.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt new file mode 100644 index 000000000000..71e39cf3215b --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |||
@@ -0,0 +1,42 @@ | |||
1 | * OpenPIC and its interrupt numbers on Freescale's e500/e600 cores | ||
2 | |||
3 | The OpenPIC specification does not specify which interrupt source has to | ||
4 | become which interrupt number. This is up to the software implementation | ||
5 | of the interrupt controller. The only requirement is that every | ||
6 | interrupt source has to have an unique interrupt number / vector number. | ||
7 | To accomplish this the current implementation assigns the number zero to | ||
8 | the first source, the number one to the second source and so on until | ||
9 | all interrupt sources have their unique number. | ||
10 | Usually the assigned vector number equals the interrupt number mentioned | ||
11 | in the documentation for a given core / CPU. This is however not true | ||
12 | for the e500 cores (MPC85XX CPUs) where the documentation distinguishes | ||
13 | between internal and external interrupt sources and starts counting at | ||
14 | zero for both of them. | ||
15 | |||
16 | So what to write for external interrupt source X or internal interrupt | ||
17 | source Y into the device tree? Here is an example: | ||
18 | |||
19 | The memory map for the interrupt controller in the MPC8544[0] shows, | ||
20 | that the first interrupt source starts at 0x5_0000 (PIC Register Address | ||
21 | Map-Interrupt Source Configuration Registers). This source becomes the | ||
22 | number zero therefore: | ||
23 | External interrupt 0 = interrupt number 0 | ||
24 | External interrupt 1 = interrupt number 1 | ||
25 | External interrupt 2 = interrupt number 2 | ||
26 | ... | ||
27 | Every interrupt number allocates 0x20 bytes register space. So to get | ||
28 | its number it is sufficient to shift the lower 16bits to right by five. | ||
29 | So for the external interrupt 10 we have: | ||
30 | 0x0140 >> 5 = 10 | ||
31 | |||
32 | After the external sources, the internal sources follow. The in core I2C | ||
33 | controller on the MPC8544 for instance has the internal source number | ||
34 | 27. Oo obtain its interrupt number we take the lower 16bits of its memory | ||
35 | address (0x5_0560) and shift it right: | ||
36 | 0x0560 >> 5 = 43 | ||
37 | |||
38 | Therefore the I2C device node for the MPC8544 CPU has to have the | ||
39 | interrupt number 43 specified in the device tree. | ||
40 | |||
41 | [0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual | ||
42 | MPC8544ERM Rev. 1 10/2007 | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt new file mode 100644 index 000000000000..bcc30bac6831 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | * Freescale MSI interrupt controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : compatible list, contains 2 entries, | ||
5 | first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, | ||
6 | etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on | ||
7 | the parent type. | ||
8 | - reg : should contain the address and the length of the shared message | ||
9 | interrupt register set. | ||
10 | - msi-available-ranges: use <start count> style section to define which | ||
11 | msi interrupt can be used in the 256 msi interrupts. This property is | ||
12 | optional, without this, all the 256 MSI interrupts can be used. | ||
13 | - interrupts : each one of the interrupts here is one entry per 32 MSIs, | ||
14 | and routed to the host interrupt controller. the interrupts should | ||
15 | be set as edge sensitive. | ||
16 | - interrupt-parent: the phandle for the interrupt controller | ||
17 | that services interrupts for this device. for 83xx cpu, the interrupts | ||
18 | are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed | ||
19 | to MPIC. | ||
20 | |||
21 | Example: | ||
22 | msi@41600 { | ||
23 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; | ||
24 | reg = <0x41600 0x80>; | ||
25 | msi-available-ranges = <0 0x100>; | ||
26 | interrupts = < | ||
27 | 0xe0 0 | ||
28 | 0xe1 0 | ||
29 | 0xe2 0 | ||
30 | 0xe3 0 | ||
31 | 0xe4 0 | ||
32 | 0xe5 0 | ||
33 | 0xe6 0 | ||
34 | 0xe7 0>; | ||
35 | interrupt-parent = <&mpic>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt new file mode 100644 index 000000000000..07256b7ffcaa --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt | |||
@@ -0,0 +1,63 @@ | |||
1 | * Power Management Controller | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "fsl,<chip>-pmc". | ||
5 | |||
6 | "fsl,mpc8349-pmc" should be listed for any chip whose PMC is | ||
7 | compatible. "fsl,mpc8313-pmc" should also be listed for any chip | ||
8 | whose PMC is compatible, and implies deep-sleep capability. | ||
9 | |||
10 | "fsl,mpc8548-pmc" should be listed for any chip whose PMC is | ||
11 | compatible. "fsl,mpc8536-pmc" should also be listed for any chip | ||
12 | whose PMC is compatible, and implies deep-sleep capability. | ||
13 | |||
14 | "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is | ||
15 | compatible; all statements below that apply to "fsl,mpc8548-pmc" also | ||
16 | apply to "fsl,mpc8641d-pmc". | ||
17 | |||
18 | Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these | ||
19 | bit assignments are indicated via the sleep specifier in each device's | ||
20 | sleep property. | ||
21 | |||
22 | - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource | ||
23 | is the PMC block, and the second resource is the Clock Configuration | ||
24 | block. | ||
25 | |||
26 | For devices compatible with "fsl,mpc8548-pmc", the first resource | ||
27 | is a 32-byte block beginning with DEVDISR. | ||
28 | |||
29 | - interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first | ||
30 | resource is the PMC block interrupt. | ||
31 | |||
32 | - fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, | ||
33 | this is a phandle to an "fsl,gtm" node on which timer 4 can be used as | ||
34 | a wakeup source from deep sleep. | ||
35 | |||
36 | Sleep specifiers: | ||
37 | |||
38 | fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit | ||
39 | that is set in the cell, the corresponding bit in SCCR will be saved | ||
40 | and cleared on suspend, and restored on resume. This sleep controller | ||
41 | supports disabling and resuming devices at any time. | ||
42 | |||
43 | fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of | ||
44 | which will be ORed into PMCDR upon suspend, and cleared from PMCDR | ||
45 | upon resume. The first two cells are as described for fsl,mpc8578-pmc. | ||
46 | This sleep controller only supports disabling devices during system | ||
47 | sleep, or permanently. | ||
48 | |||
49 | fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the | ||
50 | first of which will be ORed into DEVDISR (and the second into | ||
51 | DEVDISR2, if present -- this cell should be zero or absent if the | ||
52 | hardware does not have DEVDISR2) upon a request for permanent device | ||
53 | disabling. This sleep controller does not support configuring devices | ||
54 | to disable during system sleep (unless supported by another compatible | ||
55 | match), or dynamically. | ||
56 | |||
57 | Example: | ||
58 | |||
59 | power@b00 { | ||
60 | compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; | ||
61 | reg = <0xb00 0x100 0xa00 0x100>; | ||
62 | interrupts = <80 8>; | ||
63 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/sec.txt b/Documentation/devicetree/bindings/powerpc/fsl/sec.txt new file mode 100644 index 000000000000..2b6f2d45c45a --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/sec.txt | |||
@@ -0,0 +1,68 @@ | |||
1 | Freescale SoC SEC Security Engines | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : Should contain entries for this and backward compatible | ||
6 | SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" | ||
7 | - reg : Offset and length of the register set for the device | ||
8 | - interrupts : the SEC's interrupt number | ||
9 | - fsl,num-channels : An integer representing the number of channels | ||
10 | available. | ||
11 | - fsl,channel-fifo-len : An integer representing the number of | ||
12 | descriptor pointers each channel fetch fifo can hold. | ||
13 | - fsl,exec-units-mask : The bitmask representing what execution units | ||
14 | (EUs) are available. It's a single 32-bit cell. EU information | ||
15 | should be encoded following the SEC's Descriptor Header Dword | ||
16 | EU_SEL0 field documentation, i.e. as follows: | ||
17 | |||
18 | bit 0 = reserved - should be 0 | ||
19 | bit 1 = set if SEC has the ARC4 EU (AFEU) | ||
20 | bit 2 = set if SEC has the DES/3DES EU (DEU) | ||
21 | bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) | ||
22 | bit 4 = set if SEC has the random number generator EU (RNG) | ||
23 | bit 5 = set if SEC has the public key EU (PKEU) | ||
24 | bit 6 = set if SEC has the AES EU (AESU) | ||
25 | bit 7 = set if SEC has the Kasumi EU (KEU) | ||
26 | bit 8 = set if SEC has the CRC EU (CRCU) | ||
27 | bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) | ||
28 | |||
29 | remaining bits are reserved for future SEC EUs. | ||
30 | |||
31 | - fsl,descriptor-types-mask : The bitmask representing what descriptors | ||
32 | are available. It's a single 32-bit cell. Descriptor type information | ||
33 | should be encoded following the SEC's Descriptor Header Dword DESC_TYPE | ||
34 | field documentation, i.e. as follows: | ||
35 | |||
36 | bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type | ||
37 | bit 1 = set if SEC supports the ipsec_esp descriptor type | ||
38 | bit 2 = set if SEC supports the common_nonsnoop desc. type | ||
39 | bit 3 = set if SEC supports the 802.11i AES ccmp desc. type | ||
40 | bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type | ||
41 | bit 5 = set if SEC supports the srtp descriptor type | ||
42 | bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type | ||
43 | bit 7 = set if SEC supports the pkeu_assemble descriptor type | ||
44 | bit 8 = set if SEC supports the aesu_key_expand_output desc.type | ||
45 | bit 9 = set if SEC supports the pkeu_ptmul descriptor type | ||
46 | bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type | ||
47 | bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type | ||
48 | |||
49 | ..and so on and so forth. | ||
50 | |||
51 | Optional properties: | ||
52 | |||
53 | - interrupt-parent : the phandle for the interrupt controller that | ||
54 | services interrupts for this device. | ||
55 | |||
56 | Example: | ||
57 | |||
58 | /* MPC8548E */ | ||
59 | crypto@30000 { | ||
60 | compatible = "fsl,sec2.1", "fsl,sec2.0"; | ||
61 | reg = <0x30000 0x10000>; | ||
62 | interrupts = <29 2>; | ||
63 | interrupt-parent = <&mpic>; | ||
64 | fsl,num-channels = <4>; | ||
65 | fsl,channel-fifo-len = <24>; | ||
66 | fsl,exec-units-mask = <0xfe>; | ||
67 | fsl,descriptor-types-mask = <0x12b0ebf>; | ||
68 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt b/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt new file mode 100644 index 000000000000..5ff76c9c57d2 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/ssi.txt | |||
@@ -0,0 +1,73 @@ | |||
1 | Freescale Synchronous Serial Interface | ||
2 | |||
3 | The SSI is a serial device that communicates with audio codecs. It can | ||
4 | be programmed in AC97, I2S, left-justified, or right-justified modes. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Compatible list, contains "fsl,ssi". | ||
8 | - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. | ||
9 | - reg: Offset and length of the register set for the device. | ||
10 | - interrupts: <a b> where a is the interrupt number and b is a | ||
11 | field that represents an encoding of the sense and | ||
12 | level information for the interrupt. This should be | ||
13 | encoded based on the information in section 2) | ||
14 | depending on the type of interrupt controller you | ||
15 | have. | ||
16 | - interrupt-parent: The phandle for the interrupt controller that | ||
17 | services interrupts for this device. | ||
18 | - fsl,mode: The operating mode for the SSI interface. | ||
19 | "i2s-slave" - I2S mode, SSI is clock slave | ||
20 | "i2s-master" - I2S mode, SSI is clock master | ||
21 | "lj-slave" - left-justified mode, SSI is clock slave | ||
22 | "lj-master" - l.j. mode, SSI is clock master | ||
23 | "rj-slave" - right-justified mode, SSI is clock slave | ||
24 | "rj-master" - r.j., SSI is clock master | ||
25 | "ac97-slave" - AC97 mode, SSI is clock slave | ||
26 | "ac97-master" - AC97 mode, SSI is clock master | ||
27 | - fsl,playback-dma: Phandle to a node for the DMA channel to use for | ||
28 | playback of audio. This is typically dictated by SOC | ||
29 | design. See the notes below. | ||
30 | - fsl,capture-dma: Phandle to a node for the DMA channel to use for | ||
31 | capture (recording) of audio. This is typically dictated | ||
32 | by SOC design. See the notes below. | ||
33 | - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. | ||
34 | This number is the maximum allowed value for SFCSR[TFWM0]. | ||
35 | - fsl,ssi-asynchronous: | ||
36 | If specified, the SSI is to be programmed in asynchronous | ||
37 | mode. In this mode, pins SRCK, STCK, SRFS, and STFS must | ||
38 | all be connected to valid signals. In synchronous mode, | ||
39 | SRCK and SRFS are ignored. Asynchronous mode allows | ||
40 | playback and capture to use different sample sizes and | ||
41 | sample rates. Some drivers may require that SRCK and STCK | ||
42 | be connected together, and SRFS and STFS be connected | ||
43 | together. This would still allow different sample sizes, | ||
44 | but not different sample rates. | ||
45 | |||
46 | Optional properties: | ||
47 | - codec-handle: Phandle to a 'codec' node that defines an audio | ||
48 | codec connected to this SSI. This node is typically | ||
49 | a child of an I2C or other control node. | ||
50 | |||
51 | Child 'codec' node required properties: | ||
52 | - compatible: Compatible list, contains the name of the codec | ||
53 | |||
54 | Child 'codec' node optional properties: | ||
55 | - clock-frequency: The frequency of the input clock, which typically comes | ||
56 | from an on-board dedicated oscillator. | ||
57 | |||
58 | Notes on fsl,playback-dma and fsl,capture-dma: | ||
59 | |||
60 | On SOCs that have an SSI, specific DMA channels are hard-wired for playback | ||
61 | and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for | ||
62 | playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for | ||
63 | playback and DMA channel 3 for capture. The developer can choose which | ||
64 | DMA controller to use, but the channels themselves are hard-wired. The | ||
65 | purpose of these two properties is to represent this hardware design. | ||
66 | |||
67 | The device tree nodes for the DMA channels that are referenced by | ||
68 | "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with | ||
69 | "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. | ||
70 | "fsl,mpc8610-dma-channel") can remain. If these nodes are left as | ||
71 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA | ||
72 | drivers (fsldma) will attempt to use them, and it will conflict with the | ||
73 | sound drivers. | ||
diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt b/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt new file mode 100644 index 000000000000..b558585b1aaf --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt | |||
@@ -0,0 +1,109 @@ | |||
1 | |||
2 | Nintendo GameCube device tree | ||
3 | ============================= | ||
4 | |||
5 | 1) The "flipper" node | ||
6 | |||
7 | This node represents the multi-function "Flipper" chip, which packages | ||
8 | many of the devices found in the Nintendo GameCube. | ||
9 | |||
10 | Required properties: | ||
11 | |||
12 | - compatible : Should be "nintendo,flipper" | ||
13 | |||
14 | 1.a) The Video Interface (VI) node | ||
15 | |||
16 | Represents the interface between the graphics processor and a external | ||
17 | video encoder. | ||
18 | |||
19 | Required properties: | ||
20 | |||
21 | - compatible : should be "nintendo,flipper-vi" | ||
22 | - reg : should contain the VI registers location and length | ||
23 | - interrupts : should contain the VI interrupt | ||
24 | |||
25 | 1.b) The Processor Interface (PI) node | ||
26 | |||
27 | Represents the data and control interface between the main processor | ||
28 | and graphics and audio processor. | ||
29 | |||
30 | Required properties: | ||
31 | |||
32 | - compatible : should be "nintendo,flipper-pi" | ||
33 | - reg : should contain the PI registers location and length | ||
34 | |||
35 | 1.b.i) The "Flipper" interrupt controller node | ||
36 | |||
37 | Represents the interrupt controller within the "Flipper" chip. | ||
38 | The node for the "Flipper" interrupt controller must be placed under | ||
39 | the PI node. | ||
40 | |||
41 | Required properties: | ||
42 | |||
43 | - compatible : should be "nintendo,flipper-pic" | ||
44 | |||
45 | 1.c) The Digital Signal Procesor (DSP) node | ||
46 | |||
47 | Represents the digital signal processor interface, designed to offload | ||
48 | audio related tasks. | ||
49 | |||
50 | Required properties: | ||
51 | |||
52 | - compatible : should be "nintendo,flipper-dsp" | ||
53 | - reg : should contain the DSP registers location and length | ||
54 | - interrupts : should contain the DSP interrupt | ||
55 | |||
56 | 1.c.i) The Auxiliary RAM (ARAM) node | ||
57 | |||
58 | Represents the non cpu-addressable ram designed mainly to store audio | ||
59 | related information. | ||
60 | The ARAM node must be placed under the DSP node. | ||
61 | |||
62 | Required properties: | ||
63 | |||
64 | - compatible : should be "nintendo,flipper-aram" | ||
65 | - reg : should contain the ARAM start (zero-based) and length | ||
66 | |||
67 | 1.d) The Disk Interface (DI) node | ||
68 | |||
69 | Represents the interface used to communicate with mass storage devices. | ||
70 | |||
71 | Required properties: | ||
72 | |||
73 | - compatible : should be "nintendo,flipper-di" | ||
74 | - reg : should contain the DI registers location and length | ||
75 | - interrupts : should contain the DI interrupt | ||
76 | |||
77 | 1.e) The Audio Interface (AI) node | ||
78 | |||
79 | Represents the interface to the external 16-bit stereo digital-to-analog | ||
80 | converter. | ||
81 | |||
82 | Required properties: | ||
83 | |||
84 | - compatible : should be "nintendo,flipper-ai" | ||
85 | - reg : should contain the AI registers location and length | ||
86 | - interrupts : should contain the AI interrupt | ||
87 | |||
88 | 1.f) The Serial Interface (SI) node | ||
89 | |||
90 | Represents the interface to the four single bit serial interfaces. | ||
91 | The SI is a proprietary serial interface used normally to control gamepads. | ||
92 | It's NOT a RS232-type interface. | ||
93 | |||
94 | Required properties: | ||
95 | |||
96 | - compatible : should be "nintendo,flipper-si" | ||
97 | - reg : should contain the SI registers location and length | ||
98 | - interrupts : should contain the SI interrupt | ||
99 | |||
100 | 1.g) The External Interface (EXI) node | ||
101 | |||
102 | Represents the multi-channel SPI-like interface. | ||
103 | |||
104 | Required properties: | ||
105 | |||
106 | - compatible : should be "nintendo,flipper-exi" | ||
107 | - reg : should contain the EXI registers location and length | ||
108 | - interrupts : should contain the EXI interrupt | ||
109 | |||
diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt new file mode 100644 index 000000000000..a7e155a023b8 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt | |||
@@ -0,0 +1,184 @@ | |||
1 | |||
2 | Nintendo Wii device tree | ||
3 | ======================== | ||
4 | |||
5 | 0) The root node | ||
6 | |||
7 | This node represents the Nintendo Wii video game console. | ||
8 | |||
9 | Required properties: | ||
10 | |||
11 | - model : Should be "nintendo,wii" | ||
12 | - compatible : Should be "nintendo,wii" | ||
13 | |||
14 | 1) The "hollywood" node | ||
15 | |||
16 | This node represents the multi-function "Hollywood" chip, which packages | ||
17 | many of the devices found in the Nintendo Wii. | ||
18 | |||
19 | Required properties: | ||
20 | |||
21 | - compatible : Should be "nintendo,hollywood" | ||
22 | |||
23 | 1.a) The Video Interface (VI) node | ||
24 | |||
25 | Represents the interface between the graphics processor and a external | ||
26 | video encoder. | ||
27 | |||
28 | Required properties: | ||
29 | |||
30 | - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi" | ||
31 | - reg : should contain the VI registers location and length | ||
32 | - interrupts : should contain the VI interrupt | ||
33 | |||
34 | 1.b) The Processor Interface (PI) node | ||
35 | |||
36 | Represents the data and control interface between the main processor | ||
37 | and graphics and audio processor. | ||
38 | |||
39 | Required properties: | ||
40 | |||
41 | - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi" | ||
42 | - reg : should contain the PI registers location and length | ||
43 | |||
44 | 1.b.i) The "Flipper" interrupt controller node | ||
45 | |||
46 | Represents the "Flipper" interrupt controller within the "Hollywood" chip. | ||
47 | The node for the "Flipper" interrupt controller must be placed under | ||
48 | the PI node. | ||
49 | |||
50 | Required properties: | ||
51 | |||
52 | - #interrupt-cells : <1> | ||
53 | - compatible : should be "nintendo,flipper-pic" | ||
54 | - interrupt-controller | ||
55 | |||
56 | 1.c) The Digital Signal Procesor (DSP) node | ||
57 | |||
58 | Represents the digital signal processor interface, designed to offload | ||
59 | audio related tasks. | ||
60 | |||
61 | Required properties: | ||
62 | |||
63 | - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp" | ||
64 | - reg : should contain the DSP registers location and length | ||
65 | - interrupts : should contain the DSP interrupt | ||
66 | |||
67 | 1.d) The Serial Interface (SI) node | ||
68 | |||
69 | Represents the interface to the four single bit serial interfaces. | ||
70 | The SI is a proprietary serial interface used normally to control gamepads. | ||
71 | It's NOT a RS232-type interface. | ||
72 | |||
73 | Required properties: | ||
74 | |||
75 | - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si" | ||
76 | - reg : should contain the SI registers location and length | ||
77 | - interrupts : should contain the SI interrupt | ||
78 | |||
79 | 1.e) The Audio Interface (AI) node | ||
80 | |||
81 | Represents the interface to the external 16-bit stereo digital-to-analog | ||
82 | converter. | ||
83 | |||
84 | Required properties: | ||
85 | |||
86 | - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai" | ||
87 | - reg : should contain the AI registers location and length | ||
88 | - interrupts : should contain the AI interrupt | ||
89 | |||
90 | 1.f) The External Interface (EXI) node | ||
91 | |||
92 | Represents the multi-channel SPI-like interface. | ||
93 | |||
94 | Required properties: | ||
95 | |||
96 | - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi" | ||
97 | - reg : should contain the EXI registers location and length | ||
98 | - interrupts : should contain the EXI interrupt | ||
99 | |||
100 | 1.g) The Open Host Controller Interface (OHCI) nodes | ||
101 | |||
102 | Represent the USB 1.x Open Host Controller Interfaces. | ||
103 | |||
104 | Required properties: | ||
105 | |||
106 | - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci" | ||
107 | - reg : should contain the OHCI registers location and length | ||
108 | - interrupts : should contain the OHCI interrupt | ||
109 | |||
110 | 1.h) The Enhanced Host Controller Interface (EHCI) node | ||
111 | |||
112 | Represents the USB 2.0 Enhanced Host Controller Interface. | ||
113 | |||
114 | Required properties: | ||
115 | |||
116 | - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci" | ||
117 | - reg : should contain the EHCI registers location and length | ||
118 | - interrupts : should contain the EHCI interrupt | ||
119 | |||
120 | 1.i) The Secure Digital Host Controller Interface (SDHCI) nodes | ||
121 | |||
122 | Represent the Secure Digital Host Controller Interfaces. | ||
123 | |||
124 | Required properties: | ||
125 | |||
126 | - compatible : should be "nintendo,hollywood-sdhci","sdhci" | ||
127 | - reg : should contain the SDHCI registers location and length | ||
128 | - interrupts : should contain the SDHCI interrupt | ||
129 | |||
130 | 1.j) The Inter-Processsor Communication (IPC) node | ||
131 | |||
132 | Represent the Inter-Processor Communication interface. This interface | ||
133 | enables communications between the Broadway and the Starlet processors. | ||
134 | |||
135 | - compatible : should be "nintendo,hollywood-ipc" | ||
136 | - reg : should contain the IPC registers location and length | ||
137 | - interrupts : should contain the IPC interrupt | ||
138 | |||
139 | 1.k) The "Hollywood" interrupt controller node | ||
140 | |||
141 | Represents the "Hollywood" interrupt controller within the | ||
142 | "Hollywood" chip. | ||
143 | |||
144 | Required properties: | ||
145 | |||
146 | - #interrupt-cells : <1> | ||
147 | - compatible : should be "nintendo,hollywood-pic" | ||
148 | - reg : should contain the controller registers location and length | ||
149 | - interrupt-controller | ||
150 | - interrupts : should contain the cascade interrupt of the "flipper" pic | ||
151 | - interrupt-parent: should contain the phandle of the "flipper" pic | ||
152 | |||
153 | 1.l) The General Purpose I/O (GPIO) controller node | ||
154 | |||
155 | Represents the dual access 32 GPIO controller interface. | ||
156 | |||
157 | Required properties: | ||
158 | |||
159 | - #gpio-cells : <2> | ||
160 | - compatible : should be "nintendo,hollywood-gpio" | ||
161 | - reg : should contain the IPC registers location and length | ||
162 | - gpio-controller | ||
163 | |||
164 | 1.m) The control node | ||
165 | |||
166 | Represents the control interface used to setup several miscellaneous | ||
167 | settings of the "Hollywood" chip like boot memory mappings, resets, | ||
168 | disk interface mode, etc. | ||
169 | |||
170 | Required properties: | ||
171 | |||
172 | - compatible : should be "nintendo,hollywood-control" | ||
173 | - reg : should contain the control registers location and length | ||
174 | |||
175 | 1.n) The Disk Interface (DI) node | ||
176 | |||
177 | Represents the interface used to communicate with mass storage devices. | ||
178 | |||
179 | Required properties: | ||
180 | |||
181 | - compatible : should be "nintendo,hollywood-di" | ||
182 | - reg : should contain the DI registers location and length | ||
183 | - interrupts : should contain the DI interrupt | ||
184 | |||
diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt new file mode 100644 index 000000000000..777abd7399d5 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/fsl-spi.txt | |||
@@ -0,0 +1,53 @@ | |||
1 | * SPI (Serial Peripheral Interface) | ||
2 | |||
3 | Required properties: | ||
4 | - cell-index : QE SPI subblock index. | ||
5 | 0: QE subblock SPI1 | ||
6 | 1: QE subblock SPI2 | ||
7 | - compatible : should be "fsl,spi". | ||
8 | - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". | ||
9 | - reg : Offset and length of the register set for the device | ||
10 | - interrupts : <a b> where a is the interrupt number and b is a | ||
11 | field that represents an encoding of the sense and level | ||
12 | information for the interrupt. This should be encoded based on | ||
13 | the information in section 2) depending on the type of interrupt | ||
14 | controller you have. | ||
15 | - interrupt-parent : the phandle for the interrupt controller that | ||
16 | services interrupts for this device. | ||
17 | |||
18 | Optional properties: | ||
19 | - gpios : specifies the gpio pins to be used for chipselects. | ||
20 | The gpios will be referred to as reg = <index> in the SPI child nodes. | ||
21 | If unspecified, a single SPI device without a chip select can be used. | ||
22 | |||
23 | Example: | ||
24 | spi@4c0 { | ||
25 | cell-index = <0>; | ||
26 | compatible = "fsl,spi"; | ||
27 | reg = <4c0 40>; | ||
28 | interrupts = <82 0>; | ||
29 | interrupt-parent = <700>; | ||
30 | mode = "cpu"; | ||
31 | gpios = <&gpio 18 1 // device reg=<0> | ||
32 | &gpio 19 1>; // device reg=<1> | ||
33 | }; | ||
34 | |||
35 | |||
36 | * eSPI (Enhanced Serial Peripheral Interface) | ||
37 | |||
38 | Required properties: | ||
39 | - compatible : should be "fsl,mpc8536-espi". | ||
40 | - reg : Offset and length of the register set for the device. | ||
41 | - interrupts : should contain eSPI interrupt, the device has one interrupt. | ||
42 | - fsl,espi-num-chipselects : the number of the chipselect signals. | ||
43 | |||
44 | Example: | ||
45 | spi@110000 { | ||
46 | #address-cells = <1>; | ||
47 | #size-cells = <0>; | ||
48 | compatible = "fsl,mpc8536-espi"; | ||
49 | reg = <0x110000 0x1000>; | ||
50 | interrupts = <53 0x2>; | ||
51 | interrupt-parent = <&mpic>; | ||
52 | fsl,espi-num-chipselects = <4>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt new file mode 100644 index 000000000000..e782add2e457 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt | |||
@@ -0,0 +1,57 @@ | |||
1 | SPI (Serial Peripheral Interface) busses | ||
2 | |||
3 | SPI busses can be described with a node for the SPI master device | ||
4 | and a set of child nodes for each SPI slave on the bus. For this | ||
5 | discussion, it is assumed that the system's SPI controller is in | ||
6 | SPI master mode. This binding does not describe SPI controllers | ||
7 | in slave mode. | ||
8 | |||
9 | The SPI master node requires the following properties: | ||
10 | - #address-cells - number of cells required to define a chip select | ||
11 | address on the SPI bus. | ||
12 | - #size-cells - should be zero. | ||
13 | - compatible - name of SPI bus controller following generic names | ||
14 | recommended practice. | ||
15 | No other properties are required in the SPI bus node. It is assumed | ||
16 | that a driver for an SPI bus device will understand that it is an SPI bus. | ||
17 | However, the binding does not attempt to define the specific method for | ||
18 | assigning chip select numbers. Since SPI chip select configuration is | ||
19 | flexible and non-standardized, it is left out of this binding with the | ||
20 | assumption that board specific platform code will be used to manage | ||
21 | chip selects. Individual drivers can define additional properties to | ||
22 | support describing the chip select layout. | ||
23 | |||
24 | SPI slave nodes must be children of the SPI master node and can | ||
25 | contain the following properties. | ||
26 | - reg - (required) chip select address of device. | ||
27 | - compatible - (required) name of SPI device following generic names | ||
28 | recommended practice | ||
29 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz | ||
30 | - spi-cpol - (optional) Empty property indicating device requires | ||
31 | inverse clock polarity (CPOL) mode | ||
32 | - spi-cpha - (optional) Empty property indicating device requires | ||
33 | shifted clock phase (CPHA) mode | ||
34 | - spi-cs-high - (optional) Empty property indicating device requires | ||
35 | chip select active high | ||
36 | |||
37 | SPI example for an MPC5200 SPI bus: | ||
38 | spi@f00 { | ||
39 | #address-cells = <1>; | ||
40 | #size-cells = <0>; | ||
41 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | ||
42 | reg = <0xf00 0x20>; | ||
43 | interrupts = <2 13 0 2 14 0>; | ||
44 | interrupt-parent = <&mpc5200_pic>; | ||
45 | |||
46 | ethernet-switch@0 { | ||
47 | compatible = "micrel,ks8995m"; | ||
48 | spi-max-frequency = <1000000>; | ||
49 | reg = <0>; | ||
50 | }; | ||
51 | |||
52 | codec@1 { | ||
53 | compatible = "ti,tlv320aic26"; | ||
54 | spi-max-frequency = <100000>; | ||
55 | reg = <1>; | ||
56 | }; | ||
57 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt new file mode 100644 index 000000000000..bd5723f0b67e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt | |||
@@ -0,0 +1,81 @@ | |||
1 | Freescale SOC USB controllers | ||
2 | |||
3 | The device node for a USB controller that is part of a Freescale | ||
4 | SOC is as described in the document "Open Firmware Recommended | ||
5 | Practice : Universal Serial Bus" with the following modifications | ||
6 | and additions : | ||
7 | |||
8 | Required properties : | ||
9 | - compatible : Should be "fsl-usb2-mph" for multi port host USB | ||
10 | controllers, or "fsl-usb2-dr" for dual role USB controllers | ||
11 | or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121 | ||
12 | - phy_type : For multi port host USB controllers, should be one of | ||
13 | "ulpi", or "serial". For dual role USB controllers, should be | ||
14 | one of "ulpi", "utmi", "utmi_wide", or "serial". | ||
15 | - reg : Offset and length of the register set for the device | ||
16 | - port0 : boolean; if defined, indicates port0 is connected for | ||
17 | fsl-usb2-mph compatible controllers. Either this property or | ||
18 | "port1" (or both) must be defined for "fsl-usb2-mph" compatible | ||
19 | controllers. | ||
20 | - port1 : boolean; if defined, indicates port1 is connected for | ||
21 | fsl-usb2-mph compatible controllers. Either this property or | ||
22 | "port0" (or both) must be defined for "fsl-usb2-mph" compatible | ||
23 | controllers. | ||
24 | - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible | ||
25 | controllers. Can be "host", "peripheral", or "otg". Default to | ||
26 | "host" if not defined for backward compatibility. | ||
27 | |||
28 | Recommended properties : | ||
29 | - interrupts : <a b> where a is the interrupt number and b is a | ||
30 | field that represents an encoding of the sense and level | ||
31 | information for the interrupt. This should be encoded based on | ||
32 | the information in section 2) depending on the type of interrupt | ||
33 | controller you have. | ||
34 | - interrupt-parent : the phandle for the interrupt controller that | ||
35 | services interrupts for this device. | ||
36 | |||
37 | Optional properties : | ||
38 | - fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the | ||
39 | port power polarity of internal PHY signal DRVVBUS is inverted. | ||
40 | - fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates | ||
41 | the PWR_FAULT signal polarity is inverted. | ||
42 | |||
43 | Example multi port host USB controller device node : | ||
44 | usb@22000 { | ||
45 | compatible = "fsl-usb2-mph"; | ||
46 | reg = <22000 1000>; | ||
47 | #address-cells = <1>; | ||
48 | #size-cells = <0>; | ||
49 | interrupt-parent = <700>; | ||
50 | interrupts = <27 1>; | ||
51 | phy_type = "ulpi"; | ||
52 | port0; | ||
53 | port1; | ||
54 | }; | ||
55 | |||
56 | Example dual role USB controller device node : | ||
57 | usb@23000 { | ||
58 | compatible = "fsl-usb2-dr"; | ||
59 | reg = <23000 1000>; | ||
60 | #address-cells = <1>; | ||
61 | #size-cells = <0>; | ||
62 | interrupt-parent = <700>; | ||
63 | interrupts = <26 1>; | ||
64 | dr_mode = "otg"; | ||
65 | phy = "ulpi"; | ||
66 | }; | ||
67 | |||
68 | Example dual role USB controller device node for MPC5121ADS: | ||
69 | |||
70 | usb@4000 { | ||
71 | compatible = "fsl,mpc5121-usb2-dr"; | ||
72 | reg = <0x4000 0x1000>; | ||
73 | #address-cells = <1>; | ||
74 | #size-cells = <0>; | ||
75 | interrupt-parent = < &ipic >; | ||
76 | interrupts = <44 0x8>; | ||
77 | dr_mode = "otg"; | ||
78 | phy_type = "utmi_wide"; | ||
79 | fsl,invert-drvvbus; | ||
80 | fsl,invert-pwr-fault; | ||
81 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt new file mode 100644 index 000000000000..fa18612f757b --- /dev/null +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | USB EHCI controllers | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "usb-ehci". | ||
5 | - reg : should contain at least address and length of the standard EHCI | ||
6 | register set for the device. Optional platform-dependent registers | ||
7 | (debug-port or other) can be also specified here, but only after | ||
8 | definition of standard EHCI registers. | ||
9 | - interrupts : one EHCI interrupt should be described here. | ||
10 | If device registers are implemented in big endian mode, the device | ||
11 | node should have "big-endian-regs" property. | ||
12 | If controller implementation operates with big endian descriptors, | ||
13 | "big-endian-desc" property should be specified. | ||
14 | If both big endian registers and descriptors are used by the controller | ||
15 | implementation, "big-endian" property can be specified instead of having | ||
16 | both "big-endian-regs" and "big-endian-desc". | ||
17 | |||
18 | Example (Sequoia 440EPx): | ||
19 | ehci@e0000300 { | ||
20 | compatible = "ibm,usb-ehci-440epx", "usb-ehci"; | ||
21 | interrupt-parent = <&UIC0>; | ||
22 | interrupts = <1a 4>; | ||
23 | reg = <0 e0000300 90 0 e0000390 70>; | ||
24 | big-endian; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt new file mode 100644 index 000000000000..299d0923537b --- /dev/null +++ b/Documentation/devicetree/bindings/xilinx.txt | |||
@@ -0,0 +1,306 @@ | |||
1 | d) Xilinx IP cores | ||
2 | |||
3 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | ||
4 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | ||
5 | of standard device types (network, serial, etc.) and miscellaneous | ||
6 | devices (gpio, LCD, spi, etc). Also, since these devices are | ||
7 | implemented within the fpga fabric every instance of the device can be | ||
8 | synthesised with different options that change the behaviour. | ||
9 | |||
10 | Each IP-core has a set of parameters which the FPGA designer can use to | ||
11 | control how the core is synthesized. Historically, the EDK tool would | ||
12 | extract the device parameters relevant to device drivers and copy them | ||
13 | into an 'xparameters.h' in the form of #define symbols. This tells the | ||
14 | device drivers how the IP cores are configured, but it requires the kernel | ||
15 | to be recompiled every time the FPGA bitstream is resynthesized. | ||
16 | |||
17 | The new approach is to export the parameters into the device tree and | ||
18 | generate a new device tree each time the FPGA bitstream changes. The | ||
19 | parameters which used to be exported as #defines will now become | ||
20 | properties of the device node. In general, device nodes for IP-cores | ||
21 | will take the following form: | ||
22 | |||
23 | (name): (generic-name)@(base-address) { | ||
24 | compatible = "xlnx,(ip-core-name)-(HW_VER)" | ||
25 | [, (list of compatible devices), ...]; | ||
26 | reg = <(baseaddr) (size)>; | ||
27 | interrupt-parent = <&interrupt-controller-phandle>; | ||
28 | interrupts = < ... >; | ||
29 | xlnx,(parameter1) = "(string-value)"; | ||
30 | xlnx,(parameter2) = <(int-value)>; | ||
31 | }; | ||
32 | |||
33 | (generic-name): an open firmware-style name that describes the | ||
34 | generic class of device. Preferably, this is one word, such | ||
35 | as 'serial' or 'ethernet'. | ||
36 | (ip-core-name): the name of the ip block (given after the BEGIN | ||
37 | directive in system.mhs). Should be in lowercase | ||
38 | and all underscores '_' converted to dashes '-'. | ||
39 | (name): is derived from the "PARAMETER INSTANCE" value. | ||
40 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | ||
41 | dropped from the parameter name, the name is converted | ||
42 | to lowercase and all underscore '_' characters are | ||
43 | converted to dashes '-'. | ||
44 | (baseaddr): the baseaddr parameter value (often named C_BASEADDR). | ||
45 | (HW_VER): from the HW_VER parameter. | ||
46 | (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). | ||
47 | |||
48 | Typically, the compatible list will include the exact IP core version | ||
49 | followed by an older IP core version which implements the same | ||
50 | interface or any other device with the same interface. | ||
51 | |||
52 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | ||
53 | |||
54 | For example, the following block from system.mhs: | ||
55 | |||
56 | BEGIN opb_uartlite | ||
57 | PARAMETER INSTANCE = opb_uartlite_0 | ||
58 | PARAMETER HW_VER = 1.00.b | ||
59 | PARAMETER C_BAUDRATE = 115200 | ||
60 | PARAMETER C_DATA_BITS = 8 | ||
61 | PARAMETER C_ODD_PARITY = 0 | ||
62 | PARAMETER C_USE_PARITY = 0 | ||
63 | PARAMETER C_CLK_FREQ = 50000000 | ||
64 | PARAMETER C_BASEADDR = 0xEC100000 | ||
65 | PARAMETER C_HIGHADDR = 0xEC10FFFF | ||
66 | BUS_INTERFACE SOPB = opb_7 | ||
67 | PORT OPB_Clk = CLK_50MHz | ||
68 | PORT Interrupt = opb_uartlite_0_Interrupt | ||
69 | PORT RX = opb_uartlite_0_RX | ||
70 | PORT TX = opb_uartlite_0_TX | ||
71 | PORT OPB_Rst = sys_bus_reset_0 | ||
72 | END | ||
73 | |||
74 | becomes the following device tree node: | ||
75 | |||
76 | opb_uartlite_0: serial@ec100000 { | ||
77 | device_type = "serial"; | ||
78 | compatible = "xlnx,opb-uartlite-1.00.b"; | ||
79 | reg = <ec100000 10000>; | ||
80 | interrupt-parent = <&opb_intc_0>; | ||
81 | interrupts = <1 0>; // got this from the opb_intc parameters | ||
82 | current-speed = <d#115200>; // standard serial device prop | ||
83 | clock-frequency = <d#50000000>; // standard serial device prop | ||
84 | xlnx,data-bits = <8>; | ||
85 | xlnx,odd-parity = <0>; | ||
86 | xlnx,use-parity = <0>; | ||
87 | }; | ||
88 | |||
89 | Some IP cores actually implement 2 or more logical devices. In | ||
90 | this case, the device should still describe the whole IP core with | ||
91 | a single node and add a child node for each logical device. The | ||
92 | ranges property can be used to translate from parent IP-core to the | ||
93 | registers of each device. In addition, the parent node should be | ||
94 | compatible with the bus type 'xlnx,compound', and should contain | ||
95 | #address-cells and #size-cells, as with any other bus. (Note: this | ||
96 | makes the assumption that both logical devices have the same bus | ||
97 | binding. If this is not true, then separate nodes should be used | ||
98 | for each logical device). The 'cell-index' property can be used to | ||
99 | enumerate logical devices within an IP core. For example, the | ||
100 | following is the system.mhs entry for the dual ps2 controller found | ||
101 | on the ml403 reference design. | ||
102 | |||
103 | BEGIN opb_ps2_dual_ref | ||
104 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | ||
105 | PARAMETER HW_VER = 1.00.a | ||
106 | PARAMETER C_BASEADDR = 0xA9000000 | ||
107 | PARAMETER C_HIGHADDR = 0xA9001FFF | ||
108 | BUS_INTERFACE SOPB = opb_v20_0 | ||
109 | PORT Sys_Intr1 = ps2_1_intr | ||
110 | PORT Sys_Intr2 = ps2_2_intr | ||
111 | PORT Clkin1 = ps2_clk_rx_1 | ||
112 | PORT Clkin2 = ps2_clk_rx_2 | ||
113 | PORT Clkpd1 = ps2_clk_tx_1 | ||
114 | PORT Clkpd2 = ps2_clk_tx_2 | ||
115 | PORT Rx1 = ps2_d_rx_1 | ||
116 | PORT Rx2 = ps2_d_rx_2 | ||
117 | PORT Txpd1 = ps2_d_tx_1 | ||
118 | PORT Txpd2 = ps2_d_tx_2 | ||
119 | END | ||
120 | |||
121 | It would result in the following device tree nodes: | ||
122 | |||
123 | opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { | ||
124 | #address-cells = <1>; | ||
125 | #size-cells = <1>; | ||
126 | compatible = "xlnx,compound"; | ||
127 | ranges = <0 a9000000 2000>; | ||
128 | // If this device had extra parameters, then they would | ||
129 | // go here. | ||
130 | ps2@0 { | ||
131 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
132 | reg = <0 40>; | ||
133 | interrupt-parent = <&opb_intc_0>; | ||
134 | interrupts = <3 0>; | ||
135 | cell-index = <0>; | ||
136 | }; | ||
137 | ps2@1000 { | ||
138 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
139 | reg = <1000 40>; | ||
140 | interrupt-parent = <&opb_intc_0>; | ||
141 | interrupts = <3 0>; | ||
142 | cell-index = <0>; | ||
143 | }; | ||
144 | }; | ||
145 | |||
146 | Also, the system.mhs file defines bus attachments from the processor | ||
147 | to the devices. The device tree structure should reflect the bus | ||
148 | attachments. Again an example; this system.mhs fragment: | ||
149 | |||
150 | BEGIN ppc405_virtex4 | ||
151 | PARAMETER INSTANCE = ppc405_0 | ||
152 | PARAMETER HW_VER = 1.01.a | ||
153 | BUS_INTERFACE DPLB = plb_v34_0 | ||
154 | BUS_INTERFACE IPLB = plb_v34_0 | ||
155 | END | ||
156 | |||
157 | BEGIN opb_intc | ||
158 | PARAMETER INSTANCE = opb_intc_0 | ||
159 | PARAMETER HW_VER = 1.00.c | ||
160 | PARAMETER C_BASEADDR = 0xD1000FC0 | ||
161 | PARAMETER C_HIGHADDR = 0xD1000FDF | ||
162 | BUS_INTERFACE SOPB = opb_v20_0 | ||
163 | END | ||
164 | |||
165 | BEGIN opb_uart16550 | ||
166 | PARAMETER INSTANCE = opb_uart16550_0 | ||
167 | PARAMETER HW_VER = 1.00.d | ||
168 | PARAMETER C_BASEADDR = 0xa0000000 | ||
169 | PARAMETER C_HIGHADDR = 0xa0001FFF | ||
170 | BUS_INTERFACE SOPB = opb_v20_0 | ||
171 | END | ||
172 | |||
173 | BEGIN plb_v34 | ||
174 | PARAMETER INSTANCE = plb_v34_0 | ||
175 | PARAMETER HW_VER = 1.02.a | ||
176 | END | ||
177 | |||
178 | BEGIN plb_bram_if_cntlr | ||
179 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | ||
180 | PARAMETER HW_VER = 1.00.b | ||
181 | PARAMETER C_BASEADDR = 0xFFFF0000 | ||
182 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | ||
183 | BUS_INTERFACE SPLB = plb_v34_0 | ||
184 | END | ||
185 | |||
186 | BEGIN plb2opb_bridge | ||
187 | PARAMETER INSTANCE = plb2opb_bridge_0 | ||
188 | PARAMETER HW_VER = 1.01.a | ||
189 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | ||
190 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | ||
191 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | ||
192 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | ||
193 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | ||
194 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | ||
195 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | ||
196 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | ||
197 | BUS_INTERFACE SPLB = plb_v34_0 | ||
198 | BUS_INTERFACE MOPB = opb_v20_0 | ||
199 | END | ||
200 | |||
201 | Gives this device tree (some properties removed for clarity): | ||
202 | |||
203 | plb@0 { | ||
204 | #address-cells = <1>; | ||
205 | #size-cells = <1>; | ||
206 | compatible = "xlnx,plb-v34-1.02.a"; | ||
207 | device_type = "ibm,plb"; | ||
208 | ranges; // 1:1 translation | ||
209 | |||
210 | plb_bram_if_cntrl_0: bram@ffff0000 { | ||
211 | reg = <ffff0000 10000>; | ||
212 | } | ||
213 | |||
214 | opb@20000000 { | ||
215 | #address-cells = <1>; | ||
216 | #size-cells = <1>; | ||
217 | ranges = <20000000 20000000 20000000 | ||
218 | 60000000 60000000 20000000 | ||
219 | 80000000 80000000 40000000 | ||
220 | c0000000 c0000000 20000000>; | ||
221 | |||
222 | opb_uart16550_0: serial@a0000000 { | ||
223 | reg = <a00000000 2000>; | ||
224 | }; | ||
225 | |||
226 | opb_intc_0: interrupt-controller@d1000fc0 { | ||
227 | reg = <d1000fc0 20>; | ||
228 | }; | ||
229 | }; | ||
230 | }; | ||
231 | |||
232 | That covers the general approach to binding xilinx IP cores into the | ||
233 | device tree. The following are bindings for specific devices: | ||
234 | |||
235 | i) Xilinx ML300 Framebuffer | ||
236 | |||
237 | Simple framebuffer device from the ML300 reference design (also on the | ||
238 | ML403 reference design as well as others). | ||
239 | |||
240 | Optional properties: | ||
241 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | ||
242 | implementations use a different resolution. | ||
243 | Default is <d#640 d#480> | ||
244 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | ||
245 | Default is <d#1024 d#480>. | ||
246 | - rotate-display (empty) : rotate display 180 degrees. | ||
247 | |||
248 | ii) Xilinx SystemACE | ||
249 | |||
250 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | ||
251 | bitstream stored on a CF card. It can also be used as a generic CF | ||
252 | interface device. | ||
253 | |||
254 | Optional properties: | ||
255 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | ||
256 | |||
257 | iii) Xilinx EMAC and Xilinx TEMAC | ||
258 | |||
259 | Xilinx Ethernet devices. In addition to general xilinx properties | ||
260 | listed above, nodes for these devices should include a phy-handle | ||
261 | property, and may include other common network device properties | ||
262 | like local-mac-address. | ||
263 | |||
264 | iv) Xilinx Uartlite | ||
265 | |||
266 | Xilinx uartlite devices are simple fixed speed serial ports. | ||
267 | |||
268 | Required properties: | ||
269 | - current-speed : Baud rate of uartlite | ||
270 | |||
271 | v) Xilinx hwicap | ||
272 | |||
273 | Xilinx hwicap devices provide access to the configuration logic | ||
274 | of the FPGA through the Internal Configuration Access Port | ||
275 | (ICAP). The ICAP enables partial reconfiguration of the FPGA, | ||
276 | readback of the configuration information, and some control over | ||
277 | 'warm boots' of the FPGA fabric. | ||
278 | |||
279 | Required properties: | ||
280 | - xlnx,family : The family of the FPGA, necessary since the | ||
281 | capabilities of the underlying ICAP hardware | ||
282 | differ between different families. May be | ||
283 | 'virtex2p', 'virtex4', or 'virtex5'. | ||
284 | |||
285 | vi) Xilinx Uart 16550 | ||
286 | |||
287 | Xilinx UART 16550 devices are very similar to the NS16550 but with | ||
288 | different register spacing and an offset from the base address. | ||
289 | |||
290 | Required properties: | ||
291 | - clock-frequency : Frequency of the clock input | ||
292 | - reg-offset : A value of 3 is required | ||
293 | - reg-shift : A value of 2 is required | ||
294 | |||
295 | vii) Xilinx USB Host controller | ||
296 | |||
297 | The Xilinx USB host controller is EHCI compatible but with a different | ||
298 | base address for the EHCI registers, and it is always a big-endian | ||
299 | USB Host controller. The hardware can be configured as high speed only, | ||
300 | or high speed/full speed hybrid. | ||
301 | |||
302 | Required properties: | ||
303 | - xlnx,support-usb-fs: A value 0 means the core is built as high speed | ||
304 | only. A value 1 means the core also supports | ||
305 | full speed devices. | ||
306 | |||