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authorMasanari Iida <standby24x7@gmail.com>2013-01-14 01:14:56 -0500
committerGrant Likely <grant.likely@secretlab.ca>2013-02-06 06:06:36 -0500
commitf21ccfa07070228e0c32dad05d1cb0d19128517c (patch)
tree89db74b67c71f31aee0e0ad793469fe787011aa7 /Documentation/devicetree/bindings/rtc
parentc0a05bf0182efdf7cd1fd8aa327e7a602360b67e (diff)
documentation/devicetree: Fix typos
Correct spelling typos within Documentation/devicetree Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'Documentation/devicetree/bindings/rtc')
-rw-r--r--Documentation/devicetree/bindings/rtc/s3c-rtc.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
index 90ec45fd33ec..7ac7259fe9ea 100644
--- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
@@ -7,7 +7,7 @@ Required properties:
7- reg: physical base address of the controller and length of memory mapped 7- reg: physical base address of the controller and length of memory mapped
8 region. 8 region.
9- interrupts: Two interrupt numbers to the cpu should be specified. First 9- interrupts: Two interrupt numbers to the cpu should be specified. First
10 interrupt number is the rtc alarm interupt and second interrupt number 10 interrupt number is the rtc alarm interrupt and second interrupt number
11 is the rtc tick interrupt. The number of cells representing a interrupt 11 is the rtc tick interrupt. The number of cells representing a interrupt
12 depends on the parent interrupt controller. 12 depends on the parent interrupt controller.
13 13