Merge tag 'phy-for_3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

Kishon writes:

Adds 3 new PHY drivers stih407, stih41x and rcar gen2 PHY. It also
includes miscellaneous cleanup of other PHY drivers.

Conflicts:
	MAINTAINERS

4 files changed, 110 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
new file mode 100644
index 000000000000..1ef8228db73b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -0,0 +1,30 @@
+ST STiH407 USB PHY controller
+
+This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
+host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.
+
+Required properties:
+- compatible            : should be "st,stih407-usb2-phy"
+- reg                   : contain the offset and length of the system configuration registers
+                          used as glue logic to control & parameter phy
+- reg-names             : the names of the system configuration registers in "reg", should be "param" and "reg"
+- st,syscfg             : sysconfig register to manage phy parameter at driver level
+- resets                : list of phandle and reset specifier pairs. There should be two entries, one
+                          for the whole phy and one for the port
+- reset-names           : list of reset signal names. Should be "global" and "port"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+usb2_picophy0: usbpicophy@f8 {
+        compatible      = "st,stih407-usb2-phy";
+        reg             = <0xf8 0x04>,  /* syscfg 5062 */
+                          <0xf4 0x04>;  /* syscfg 5061 */
+        reg-names       = "param", "ctrl";
+        #phy-cells      = <0>;
+        st,syscfg       = <&syscfg_core>;
+        resets          = <&softreset STIH407_PICOPHY_SOFTRESET>,
+                          <&picophyreset STIH407_PICOPHY0_RESET>;
+        reset-names     = "global", "port";
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
new file mode 100644
index 000000000000..00944a05ee6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
@@ -0,0 +1,24 @@
+STMicroelectronics STiH41x USB PHY binding
+------------------------------------------
+
+This file contains documentation for the usb phy found in STiH415/6 SoCs from
+STMicroelectronics.
+
+Required properties:
+- compatible    : should be "st,stih416-usb-phy" or "st,stih415-usb-phy"
+- st,syscfg     : should be a phandle of the syscfg node
+- clock-names   : must contain "osc_phy"
+- clocks        : must contain an entry for each name in clock-names.
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- #phy-cells    : must be 0 for this phy
+See: Documentation/devicetree/bindings/phy/phy-bindings.txt
+
+Example:
+
+usb2_phy: usb2phy@0 {
+        compatible      = "st,stih416-usb-phy";
+        #phy-cell       = <0>;
+        st,syscfg       = <&syscfg_rear>;
+        clocks          = <&clk_sysin>;
+        clock-names     = "osc_phy";
+};
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
new file mode 100644
index 000000000000..00fc52a034b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
@@ -0,0 +1,51 @@
+* Renesas R-Car generation 2 USB PHY
+
+This file provides information on what the device node for the R-Car generation
+2 USB PHY contains.
+
+Required properties:
+- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+              "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
+- reg: offset and length of the register block.
+- #address-cells: number of address cells for the USB channel subnodes, must
+                  be <1>.
+- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be "usbhs".
+
+The USB PHY device tree node should have the subnodes corresponding to the USB
+channels. These subnodes must contain the following properties:
+- reg: the USB controller selector; see the table below for the values.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
+
+The phandle's argument in the PHY specifier is the USB controller selector for
+the USB channel; see the selector meanings below:
+
++-----------+---------------+---------------+
+|\ Selector |               |               |
++ --------- +       0       |       1       |
+| Channel  \|               |               |
++-----------+---------------+---------------+
+| 0         | PCI EHCI/OHCI | HS-USB        |
+| 2         | PCI EHCI/OHCI | xHCI          |
++-----------+---------------+---------------+
+
+Example (Lager board):
+
+        usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7790";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                clock-names = "usbhs";
+
+                usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 7a6feea2a48b..15e0f2c7130f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -17,8 +17,11 @@ Samsung EXYNOS SoC series Display Port PHY
 -------------------------------------------------
 
 Required properties:
-- compatible : should be "samsung,exynos5250-dp-video-phy";
-- reg : offset and length of the Display Port PHY register set;
+- compatible : should be one of the following supported values:
+         - "samsung,exynos5250-dp-video-phy"
+         - "samsung,exynos5420-dp-video-phy"
+- samsung,pmu-syscon: phandle for PMU system controller interface, used to
+                      control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 0;
 
 Samsung S5P/EXYNOS SoC series USB PHY