diff options
author | Thierry Reding <treding@nvidia.com> | 2013-11-15 10:06:05 -0500 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2014-04-04 03:12:50 -0400 |
commit | 6b6b604215c64666fbf0fed939a5c312cc7b12fe (patch) | |
tree | 965dec0ece2b01700f4f68b4e75542219ee37bec /Documentation/devicetree/bindings/gpu | |
parent | 64400c3791d9fcebf23318a289f9da964547a6f3 (diff) |
drm/tegra: Add eDP support
Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/gpu')
-rw-r--r-- | Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index efaeec8961b6..efa8b8451f93 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | |||
@@ -190,6 +190,48 @@ of the following host1x client modules: | |||
190 | - nvidia,edid: supplies a binary EDID blob | 190 | - nvidia,edid: supplies a binary EDID blob |
191 | - nvidia,panel: phandle of a display panel | 191 | - nvidia,panel: phandle of a display panel |
192 | 192 | ||
193 | - sor: serial output resource | ||
194 | |||
195 | Required properties: | ||
196 | - compatible: "nvidia,tegra124-sor" | ||
197 | - reg: Physical base address and length of the controller's registers. | ||
198 | - interrupts: The interrupt outputs from the controller. | ||
199 | - clocks: Must contain an entry for each entry in clock-names. | ||
200 | See ../clocks/clock-bindings.txt for details. | ||
201 | - clock-names: Must include the following entries: | ||
202 | - sor: clock input for the SOR hardware | ||
203 | - parent: input for the pixel clock | ||
204 | - dp: reference clock for the SOR clock | ||
205 | - safe: safe reference for the SOR clock during power up | ||
206 | - resets: Must contain an entry for each entry in reset-names. | ||
207 | See ../reset/reset.txt for details. | ||
208 | - reset-names: Must include the following entries: | ||
209 | - sor | ||
210 | |||
211 | Optional properties: | ||
212 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
213 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
214 | - nvidia,edid: supplies a binary EDID blob | ||
215 | - nvidia,panel: phandle of a display panel | ||
216 | |||
217 | Optional properties when driving an eDP output: | ||
218 | - nvidia,dpaux: phandle to a DispayPort AUX interface | ||
219 | |||
220 | - dpaux: DisplayPort AUX interface | ||
221 | - compatible: "nvidia,tegra124-dpaux" | ||
222 | - reg: Physical base address and length of the controller's registers. | ||
223 | - interrupts: The interrupt outputs from the controller. | ||
224 | - clocks: Must contain an entry for each entry in clock-names. | ||
225 | See ../clocks/clock-bindings.txt for details. | ||
226 | - clock-names: Must include the following entries: | ||
227 | - dpaux: clock input for the DPAUX hardware | ||
228 | - parent: reference clock | ||
229 | - resets: Must contain an entry for each entry in reset-names. | ||
230 | See ../reset/reset.txt for details. | ||
231 | - reset-names: Must include the following entries: | ||
232 | - dpaux | ||
233 | - vdd-supply: phandle of a supply that powers the DisplayPort link | ||
234 | |||
193 | Example: | 235 | Example: |
194 | 236 | ||
195 | / { | 237 | / { |