diff options
author | Paul Walmsley <paul@pwsan.com> | 2015-01-30 17:11:04 -0500 |
---|---|---|
committer | Rob Herring <robh@kernel.org> | 2015-02-03 21:37:31 -0500 |
commit | 193c9d23a0f0b8ae0c2aeb517c953ba8aee4ceb9 (patch) | |
tree | 9508950b34a6f7723da6f9a3488897de99306583 /Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | |
parent | 2d4c0aef0ff4d4374590d6c7b259a259bb2cb21b (diff) |
Documentation: DT bindings: add more Tegra chip compatible strings
Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:
http://marc.info/?l=devicetree&m=142255654213019&w=2
The primary objective here is to avoid checkpatch warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
DT binding text files have been updated for the following IP blocks:
- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY
N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.
This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:
- Per-IP block patches have been combined into a single patch
- Explicit documentation about which compatible strings are actually
matched by the driver has been removed. In its place is implicit
documentation that loosely follows Rob's prescribed format:
"Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
<chip> is tegra30, tegra132, ..." [...] "You should attempt to
document known values of <chip> if you use it"
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt')
-rw-r--r-- | Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index 4c32ef0b7db8..009f4bfa1590 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | |||
@@ -197,7 +197,9 @@ of the following host1x client modules: | |||
197 | - sor: serial output resource | 197 | - sor: serial output resource |
198 | 198 | ||
199 | Required properties: | 199 | Required properties: |
200 | - compatible: "nvidia,tegra124-sor" | 200 | - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise, |
201 | must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip> | ||
202 | is tegra132. | ||
201 | - reg: Physical base address and length of the controller's registers. | 203 | - reg: Physical base address and length of the controller's registers. |
202 | - interrupts: The interrupt outputs from the controller. | 204 | - interrupts: The interrupt outputs from the controller. |
203 | - clocks: Must contain an entry for each entry in clock-names. | 205 | - clocks: Must contain an entry for each entry in clock-names. |
@@ -222,7 +224,9 @@ of the following host1x client modules: | |||
222 | - nvidia,dpaux: phandle to a DispayPort AUX interface | 224 | - nvidia,dpaux: phandle to a DispayPort AUX interface |
223 | 225 | ||
224 | - dpaux: DisplayPort AUX interface | 226 | - dpaux: DisplayPort AUX interface |
225 | - compatible: "nvidia,tegra124-dpaux" | 227 | - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise, |
228 | must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where | ||
229 | <chip> is tegra132. | ||
226 | - reg: Physical base address and length of the controller's registers. | 230 | - reg: Physical base address and length of the controller's registers. |
227 | - interrupts: The interrupt outputs from the controller. | 231 | - interrupts: The interrupt outputs from the controller. |
228 | - clocks: Must contain an entry for each entry in clock-names. | 232 | - clocks: Must contain an entry for each entry in clock-names. |