MIPS: Octeon: Add device tree source files.

The two device tree files octeon_3xxx.dts and octeon_68xx.dts are
trimmed by code in a subsequent patch to reflect the hardware actually
present on the board.  To this end several properties that are not
part of the declared bindings are added to aid in trimming off
unwanted nodes.  Since the device tree and the code that trims it are
bound into the kernel binary, these 'marker' properties never escape
into the wild, and are purely an implementation detail of the kernel
early boot process.  This is done for backwards compatibility with
existing boards (identified by a board type enumeration value by their
bootloaders).  New boards will always pass a device tree from the
bootloader, the built-in trees are ignored in this case.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/3937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 49 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
new file mode 100644
index 000000000000..9d6dcd3fe7f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
@@ -0,0 +1,49 @@
+* General Purpose Input Output (GPIO) bus.
+
+Properties:
+- compatible: "cavium,octeon-3860-gpio"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the GPIO unit's register bank.
+
+- gpio-controller: This is a GPIO controller.
+
+- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.
+
+- interrupt-controller: The GPIO controller is also an interrupt
+  controller, many of its pins may be configured as an interrupt
+  source.
+
+- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin
+   connected to the interrupt source.  The second cell is the interrupt
+   triggering protocol and may have one of four values:
+   1 - edge triggered on the rising edge.
+   2 - edge triggered on the falling edge
+   4 - level triggered active high.
+   8 - level triggered active low.
+
+- interrupts: Interrupt routing for each pin.
+
+Example:
+
+        gpio-controller@1070000000800 {
+                #gpio-cells = <2>;
+                compatible = "cavium,octeon-3860-gpio";
+                reg = <0x10700 0x00000800 0x0 0x100>;
+                gpio-controller;
+                /* Interrupts are specified by two parts:
+                 * 1) GPIO pin number (0..15)
+                 * 2) Triggering (1 - edge rising
+                 *                2 - edge falling
+                 *                4 - level active high
+                 *                8 - level active low)
+                 */
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                /* The GPIO pin connect to 16 consecutive CUI bits */
+                interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
+                             <0 20>, <0 21>, <0 22>, <0 23>,
+                             <0 24>, <0 25>, <0 26>, <0 27>,
+                             <0 28>, <0 29>, <0 30>, <0 31>;
+        };