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authorStephen Warren <swarren@nvidia.com>2013-08-09 12:57:46 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-08-15 16:12:46 -0400
commita1bc260bb5f5d95da854be7898202d788e94448d (patch)
treeffe534194e65339554e37dfcd82af06e5335f749 /Documentation/devicetree/bindings/gpio
parent0fabc8354318f84efd942fe3017fff2326392094 (diff)
gpio: clean up gpio-ranges documentation
This change makes documentation of the the gpio-ranges property shorter and more succinct, more consistent with the style of the rest of the document, and not mention Linux-specifics such as the API pinctrl_request_gpio(); DT binding documents should be OS independant where at all possible. As part of this, the gpio-ranges property's format is described in BNF form, in order to match the rest of the document. This change also deprecates the #gpio-range-cells property. Such properties are useful when one node references a second node, and that second node dictates the format of the reference. However, that is not the case here; the definition of gpio-ranges itself always dictates its format entirely, and hence the value #gpio-range-cells must always be 3, and hence there is no point requiring any referenced node to include this property. The only remaining need for this property is to ensure compatibility of DTs with older SW that was written to support the previous version of the binding. v4: * Mention #gpio-range-cells as being deprecated, rather than removing all documentation of that property. This allows DTs to be written in a backwards-compatible way if desired, and also allows older DTs to be interpreted fully using the latest documentation. v3: * Mention BNF in commit description. * Fixed typo. * Dropped patch that removed the deprecated property from *.dts, since it's required to boot older kernels. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio.txt55
1 files changed, 30 insertions, 25 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index d933af370697..6cec6ff20d2e 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -75,23 +75,36 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
75 gpio-controller; 75 gpio-controller;
76 }; 76 };
77 77
782.1) gpio-controller and pinctrl subsystem 782.1) gpio- and pin-controller interaction
79------------------------------------------ 79-----------------------------------------
80 80
81gpio-controller on a SOC might be tightly coupled with the pinctrl 81Some or all of the GPIOs provided by a GPIO controller may be routed to pins
82subsystem, in the sense that the pins can be used by other functions 82on the package via a pin controller. This allows muxing those pins between
83together with optional gpio feature. 83GPIO and other functions.
84 84
85While the pin allocation is totally managed by the pin ctrl subsystem, 85It is useful to represent which GPIOs correspond to which pins on which pin
86gpio (under gpiolib) is still maintained by gpio drivers. It may happen 86controllers. The gpio-ranges property described below represents this, and
87that different pin ranges in a SoC is managed by different gpio drivers. 87contains information structures as follows:
88 88
89This makes it logical to let gpio drivers announce their pin ranges to 89 gpio-range-list ::= <single-gpio-range> [gpio-range-list]
90the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to 90 single-gpio-range ::=
91request the corresponding pin before any gpio usage. 91 <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
92 gpio-phandle : phandle to pin controller node.
93 gpio-base : Base GPIO ID in the GPIO controller
94 pinctrl-base : Base pinctrl pin ID in the pin controller
95 count : The number of GPIOs/pins in this range
92 96
93For this, the gpio controller can use a pinctrl phandle and pins to 97The "pin controller node" mentioned above must conform to the bindings
94announce the pinrange to the pin ctrl subsystem. For example, 98described in ../pinctrl/pinctrl-bindings.txt.
99
100Previous versions of this binding required all pin controller nodes that
101were referenced by any gpio-ranges property to contain a property named
102#gpio-range-cells with value <3>. This requirement is now deprecated.
103However, that property may still exist in older device trees for
104compatibility reasons, and would still be required even in new device
105trees that need to be compatible with older software.
106
107Example:
95 108
96 qe_pio_e: gpio-controller@1460 { 109 qe_pio_e: gpio-controller@1460 {
97 #gpio-cells = <2>; 110 #gpio-cells = <2>;
@@ -99,16 +112,8 @@ announce the pinrange to the pin ctrl subsystem. For example,
99 reg = <0x1460 0x18>; 112 reg = <0x1460 0x18>;
100 gpio-controller; 113 gpio-controller;
101 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; 114 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
115 };
102 116
103 } 117Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
104 118pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
105where, 119pins 50..59.
106 &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
107
108 Next values specify the base pin and number of pins for the range
109 handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
110 pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
111 pinctrl2 with gpio offset 10 is handled by this gpio controller.
112
113The pinctrl node must have "#gpio-range-cells" property to show number of
114arguments to pass with phandle from gpio controllers node.