diff options
author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-02-17 06:42:47 -0500 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2013-03-06 23:27:29 -0500 |
commit | 86853c83e33738397564e9377ceeff94d4bc041c (patch) | |
tree | 94b4df911227c48b62ace647d0989a2b4da0d019 /Documentation/devicetree/bindings/gpio | |
parent | e3929714942b242ecb55657e70d51e0eb4c77726 (diff) |
gpio: add gpio offset in gpio range cells property
Add gpio offset into "gpio-range-cells" property. It's used to support
sparse pinctrl range in gpio chip.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r-- | Documentation/devicetree/bindings/gpio/gpio.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a33628759d36..d933af370697 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, | |||
98 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | 98 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; |
99 | reg = <0x1460 0x18>; | 99 | reg = <0x1460 0x18>; |
100 | gpio-controller; | 100 | gpio-controller; |
101 | gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; | 101 | gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; |
102 | 102 | ||
103 | } | 103 | } |
104 | 104 | ||
@@ -107,8 +107,8 @@ where, | |||
107 | 107 | ||
108 | Next values specify the base pin and number of pins for the range | 108 | Next values specify the base pin and number of pins for the range |
109 | handled by 'qe_pio_e' gpio. In the given example from base pin 20 to | 109 | handled by 'qe_pio_e' gpio. In the given example from base pin 20 to |
110 | pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled | 110 | pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under |
111 | by this gpio controller. | 111 | pinctrl2 with gpio offset 10 is handled by this gpio controller. |
112 | 112 | ||
113 | The pinctrl node must have "#gpio-range-cells" property to show number of | 113 | The pinctrl node must have "#gpio-range-cells" property to show number of |
114 | arguments to pass with phandle from gpio controllers node. | 114 | arguments to pass with phandle from gpio controllers node. |